NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
First Claim
1. A nonvolatile semiconductor memory device comprising:
- a plurality of word lines;
a plurality of bit lines;
a plurality of sense amplifiers, each amplifier being connected to one of said plurality of bit lines respectively; and
a memory cell array including a memory cell region including a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, each of said memory cells having two or more storage states, said plurality of memory cells being connected to a corresponding word line of said plurality of word lines respectively, said plurality of memory strings being connected to a corresponding bit line of said plurality of bit lines respectively, and at the time of programming all of said plurality of bit lines are selected, the number of said storage states being different in two of said memory cells which are adjacent on the same bit line.
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Accused Products
Abstract
A nonvolatile semiconductor memory device having a plurality of word lines and a plurality of bit lines and a plurality of sense amplifiers, each amplifier being connected to one of the plurality of bit lines respectively and a memory cell array including a memory cell region including a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, each of the memory cells having two or more storage states, said plurality of memory cells being connected to a corresponding word line of the plurality of word lines respectively, the plurality of memory strings being connected to a corresponding bit line of the plurality of bit lines respectively, and at the time of programming all of the plurality of bit lines are selected, the number of the storage states being different in two of the memory cells which are adjacent on the same bit line.
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Citations
20 Claims
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1. A nonvolatile semiconductor memory device comprising:
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a plurality of word lines; a plurality of bit lines; a plurality of sense amplifiers, each amplifier being connected to one of said plurality of bit lines respectively; and a memory cell array including a memory cell region including a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, each of said memory cells having two or more storage states, said plurality of memory cells being connected to a corresponding word line of said plurality of word lines respectively, said plurality of memory strings being connected to a corresponding bit line of said plurality of bit lines respectively, and at the time of programming all of said plurality of bit lines are selected, the number of said storage states being different in two of said memory cells which are adjacent on the same bit line. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A nonvolatile semiconductor memory device comprising:
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a plurality of word lines having odd word lines and even word lines; a plurality of bit lines; a plurality of sense amplifiers, each amplifier being connected to one of said plurality of bit lines respectively; and
a memory cell array including a memory cell region including a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, each of said memory cells having two or more storage states, said plurality of memory cells being connected to a corresponding word line of said plurality of word lines respectively, said plurality of memory strings being connected to a corresponding bit line of said plurality of bit lines respectively, and at the time of programming all of said plurality of bit lines are selected, the number of said storage states of said memory cells connected to said odd word lines is different from the number of said storage states of said memory cells connected to said even word lines. - View Dependent Claims (9, 10, 11, 12)
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13. A nonvolatile semiconductor memory device comprising:
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a plurality of word lines; a plurality of bit lines; a plurality of sense amplifiers, each amplifier being connected to one of said plurality of bit lines respectively; and a memory cell array including a memory cell region including a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, each of said memory cells having two or more storage states, said plurality of memory cells being connected to a corresponding word line of said plurality of word lines respectively, said plurality of memory strings being connected to a corresponding bit line of said plurality of bit lines respectively, each of first addresses being allocated to one of said plurality of said memory cells, each of second addresses being allocated to two of said plurality of memory cells which are adjacent on the same bit line, said memory cell being selected by a corresponding first address of said first addresses and a corresponding second address of said second addresses, and at the time of programming all of said plurality of bit lines are selected, the number of said storage states being different in two of said memory cells which are adjacent on the same bit line. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification