HYBRID NON-VOLATILE MEMORY
3 Assignments
0 Petitions
Accused Products
Abstract
A non-volatile memory (NVM) circuit includes at least two types of NVM sub-circuits that share common support circuitry. Different types of NVM sub-circuits include ordinary NVM circuits that provide a logic output upon being addressed, programmable fuses that provide an output upon transitioning to a power-on state, NVM circuits that provide an ON/OFF state output, and the like. Some of the outputs are used to calibrate circuits within a device following power-on. Other outputs are used to store information to be employed by various circuits.
106 Citations
69 Claims
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1-43. -43. (canceled)
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44. A hybrid Non-Volatile Memory (NVM) device, comprising:
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a first circuit of a first type NVM cell for storing data for a first operational component; a second circuit of a second type NVM cell that is different from the first type NVM cell, wherein the second circuit is for storing data for a second operational component distinct from the first operational component, and wherein the second circuit is distinct from the first operational component; and support circuitry, wherein a portion of the support circuitry is arranged to support the first circuit and the second circuit. - View Dependent Claims (45, 46, 47, 48, 49, 50, 51, 52)
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53. A hybrid NVM device, comprising:
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a first circuit for storing data for a first operational component, wherein the first circuit includes a plurality of NVM array bits arranged in rows and columns of an NVM array, and wherein a first portion of the NVM array bits are arranged to output their stored logic value faster than a second portion of the NVM array bits during a power-on state; a second circuit that includes at least one NVM cell arranged to provide an output upon transitioning to a power-on state, wherein the second circuit is for storing data for a second operational component distinct from the first operational component, and wherein the second circuit is distinct from the first operational component; support circuitry, wherein a portion of the support circuitry is shared by the first circuit and the second circuit; and
wherein the support circuitry include an addressing circuit that is arranged to cause the second portion of the NVM array bits to output their stored logic value in the power-on state. - View Dependent Claims (54, 55, 56, 57)
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58. A method for a hybrid NVM device, comprising:
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storing a plurality of values in a plurality of NVM cells, wherein the NVM cells are adapted to store the values even during a power-off state; outputting a first portion of NVM cells for a first operational component upon powering support circuitry; and outputting a second portion of NVM cells for a second operational component distinct from the first operational component upon being addressed by the support circuitry, wherein a circuit for outputting a second portion of NVM cells is distinct from the first operational component and wherein the support circuitry is shared by the first portion of NVM cells and the second portion of NVM cells. - View Dependent Claims (59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69)
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Specification