Decoding control with address transition detection in page erase function

• US 20080205164A1
• Filed: 02/27/2007
• Published: 08/28/2008
• Est. Priority Date: 02/27/2007
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Pyeon, Hong Beom
• Granted Patent: US 7,577,059 B2
• Time in Patent Office: Days
• US Class Current: 365/185.29
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/20 Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access

Abstract

Circuits and methods are provided for controlling multi-page erase operations in flash memory. The page address of each address of a multi-page erase operation is latched in wordline decoders. A page select reset generator circuit processes the block addresses of each address of the multi-page erase operation. In the event the addresses relate to pages in different blocks, then previously latched page addresses are reset. This avoids the incorrect circuit operation that will result should a multi-page erase operation include multiple pages in different blocks.

Claims

1. A page select reset generator circuit for limiting multi-page erase operations in non-volatile memory, the page select reset generator circuit comprising:

an input for receiving block address portions of each address of a set of one or more addresses;

an address transition detect circuit that detects when block address portions of two addresses of the set of page addresses are different;

the page select reset generator being operable to generate a reset output for clearing latched pages upon detecting that block address portions of two addresses are different.

2. The page select reset generator circuit of claim 1, for limiting multi-page erase operations in non-volatile memory that is flash memory.

3. The page select reset generator circuit of claim 1 further comprising:

a first page select reset enable circuit that enables the generation of the reset output when the addresses are in respect of multi-page erase operation.

4. The page select reset generator circuit of claim 1 further comprising:

a second page select reset enable circuit that enables the generation of the reset output timed properly with the latching of addresses in main address registers.

5. The page select reset generator circuit of claim 1 further comprising:

a first page select reset enable circuit that enables the generation of the reset output when the page addresses are in respect of multi-page erase operation;

a second page select reset enable circuit that enables the generation of the reset output timed properly with the latching of addresses in main address registers;

wherein the page select reset generator is operable to generate the reset output only when enabled by both the first page select reset enable circuit and the second page select reset enable circuit.

6. The page select reset generator circuit of claim 1 wherein the address transition detect circuit comprises:

for each bit of a multi-bit block address;

a) a respective sub-address register for registering the bit and producing a registered address output;

b) a respective bitwise address detection circuit for detecting a transition in the registered address output;

a merger circuit for combining outputs of the bitwise address detection circuits.

7. The page select reset generator circuit of claim 6 wherein each bitwise address detection circuit comprises:

a first circuit for detecting rising address transitions;

a second circuit for detecting falling address transitions;

a circuit for combining outputs of the first circuit and the second circuit.

8. The page select reset generator circuit of claim 7 wherein:

the first circuit for detecting rising address transitions comprises;

a) an inverter and a delay element connected together in sequence;

b) a NAND gate having a first input connected to receive one of the registered address outputs, the NAND gate having a second input connected to receive the one of the registered address outputs after inversion by the inverter and delay by the delay element;

the second circuit for detecting falling address transitions comprises;

a) an inverter and a delay element;

b) a NAND gate having a first input connected to receive one of the registered address outputs after inversion by the inverter, the NAND gate having a second input connected to receive the one of the registered address outputs after delay by the delay element.

9. The page select reset generator circuit of claim 6 wherein for each bit of the multi-bit block address, the respective sub-address register comprises:

an SR latch having an input connected to receive the bit;

an enable circuit for enabling latching of the bit to the SR that enables the generation of the reset output when the page addresses are in respect of multi-page erase operation.

10. The page select reset generator circuit of claim 7 further comprising:

a main reset pulse generator circuit.

11. A memory circuit comprising:

a plurality of memory blocks each block comprising non-volatile memory cells arranged in a plurality of pages;

a respective latching circuit for each page, each page having a page address, the page addresses of the pages being unique within each block, the page address of each page being the same as that of a corresponding page in each other block;

a respective block enable circuit for each block;

a block pre-decoder circuit that processes a block address portion of each address of a page erase command by enabling the block enable circuit for the block identified by the block address portion of the address;

a page pre-decoder circuit that processes a page address portion of each address of a page erase command by setting the latching circuit for each page having the page address identified by the address portion;

the page select reset generator circuit of claim 1;

the latching circuits being further operable to connect an erase voltage to the selected pages of the enabled blocks after all addresses of the page erase command have been processed by the block pre-decoder, the page pre-decoder, and the page select reset generator circuit;

wherein accidental erasure of pages due to a multi-page erase operation relating to two or more different block addresses is prevented.

12. The memory circuit of claim 11 wherein the non-volatile memory is flash memory.

13. The memory circuit of claim 11 wherein the latching circuits have a commonly connected reset input for receiving the reset output generated by the page select reset generator.

14. A method comprising:

for each of a plurality of addresses of a multi-page erase operation pertaining to a non-volatile memory, each address containing a block address portion and a page address portion;

a) detecting whether the block address portion differs from that of a previous address of the plurality of addresses;

b) resetting any previous selections of pages and blocks upon detecting that the block address differs from that of a previous address of the plurality of addresses;

c) selecting a respective page in each of a plurality of blocks;

d) selecting a respective one of the plurality of blocks; and

wherein after said detecting, resetting, selecting a respective page, and selecting a respective one of the plurality of blocks on each address, a single remaining block address will be selected, the method further comprising erasing any selected pages in the single remaining selected block.

15. The method of claim 14 further comprising:

generating a reset output to reset the previous selections.

16. The method of claim 15 further comprising:

receiving addresses, each address containing a block portion and a page address portion;

for each received address, determining if the address is part of a page erase operation;

performing said detecting and resetting only if the address is determined to be part of a page erase operation.

17. The method of claim 15 further comprising;

latching addresses in main address registers;

timing the generation of the reset output with the latching of addresses in main address registers.

18. The method of claim 14 wherein detecting whether the block address portion differs from that of a previous address of the plurality of addresses comprises:

for each bit of a multi-bit block address;

a) registering the bit into a respective sub-address register;

b) performing bitwise address detection to detect a transition in an output of the sub-address register;

combining outputs of the bitwise address detection.

19. The method of claim 18 wherein performing bitwise address detection comprises:

detecting rising address transitions; and

detecting falling address transitions.

20. The method of claim 14 applied to flash memory.