APPARATUS AND METHOD FOR USING A PAGE BUFFER OF A MEMORY DEVICE AS A TEMPORARY CACHE

• US 20080205168A1
• Filed: 02/12/2008
• Published: 08/28/2008
• Est. Priority Date: 02/22/2007
• Status: Active Grant

• Current Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: OH, HakJune, PYEON, Hong Beom, KIM, Jin-Ki
• Granted Patent: US 8,046,527 B2
• Time in Patent Office: Days
• US Class Current: 365/189.14
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 13/4247 on a daisy chain bus

Abstract

An apparatus and method are provided for using a page buffer of a memory device as a temporary cache for data. A memory controller writes data to the page buffer and later reads out the data without programming the data into the memory cells of the memory device. This allows the memory controller to use the page buffer as temporary cache so that the data does not have to occupy space within the memory controller'"'"'s local data storage elements. Therefore, the memory controller can use the space in its own storage elements for other operations.

Claims

1. A method for communicating with a plurality of memory devices connected in-series, at least one of the memory devices having a temporary store element, the method comprising:

selecting a memory device of the plurality of memory devices,

writing data stored in a data storage to the temporary store element of the selected memory device; and

at a later time, reading the data from the temporary store element of the selected memory device.

2. The method of claim 1 further comprising

storing the read data back to the data storage.

3. The method of claim 1 further comprising:

freeing up space storing the data in the data storage after performing the step of writing.

4. The method of claim 1 wherein the step of writing comprises:

transmitting a write command including the data addressed to the selected memory device, the selected device writing the data to the temporary store element thereof in response to the write command.

5. The method of claim 4 wherein the step of reading comprises:

transmitting a read command addressed to the selected memory device, the selected memory device reading the data from the temporary store element thereof in response to the read command; and

receiving the read data through the last memory device of plurality of memory devices.

6. The method of claim 5 wherein:

the step of transmitting a write command comprises transmitting the write command including a device address;

the step of selecting comprises determining whether the device address of the write command matches that of the selected memory device, in a case of device address matching, the data being written into the temporary store element of the selected memory device; and

the step of transmitting a read command comprises transmitting the read command including a device address, in a case of device address matching, the data being read from the temporary store element of the selected memory device.

7. The method of claim 5 further comprising:

selecting another memory device of the plurality of memory devices.

8. The method of claim 7 further comprising:

writing the data to the temporary store element of the another selected memory device.

9. The method of claim 8 further comprising:

storing the data in the data storage, the stored data comprising a plurality of data parts including first and second data parts.

10. The method of claim 9 wherein:

the step of writing data to the selected memory device comprises writing the first data part to the temporary store element of the selected memory device; and

the step of writing data to the selected another memory device comprises writing the second data part to the temporary store element of the selected another memory device.

11. The method of claim 10 wherein the step of reading comprises:

reading the first data part from the temporary store element of the selected memory device; and

reading the second data part from the temporary store element of the selected another memory device.

12. The method of claim 9 wherein:

the steps of selecting another memory device and writing another data to the temporary store element of the another selected memory device are performed later than the steps of selecting a memory device and writing data to the temporary store element of the selected memory device.

13. The method of claim 9 wherein:

the steps of selecting another memory device and writing another data to the temporary store element of the another selected memory device are performed later than the steps of selecting a memory device and writing data to the temporary store element of the selected memory device.

14. The method of claim 1 wherein the step of selecting comprises:

sending a device address to the memory devices that determine address match in response to the sent device address.

15. An apparatus in communication with a plurality of memory devices connected in-series, each of the memory devices having a temporary store element, the apparatus comprising:

a processor for

selecting a memory device of the plurality of memory devices,

writing data in the temporary store element of the selected memory device; and

reading back the data at a later time from the temporary store element of the selected memory device.

16. The apparatus of claim 15 wherein the processor comprises:

a storage element for storing the data to be written in the temporary store element of the selected memory device,

the processor being configured to free up space in the storage element where the data is stored upon writing the data to the temporary store element of the selected memory device.

17. The apparatus of claim 15 wherein the processor is further configured to store the data back into the storage element upon reading back the data from the temporary store element of the selected memory device.

18. The apparatus of claim 16 wherein the processor is further configured to:

select another memory device of the plurality of memory devices;

write the data to the temporary store element of the selected another memory device; and

read back the data at a later time from the temporary store element of the selected another memory device.

19. The apparatus of claim 18 wherein the processor is further configured to free up space in the storage element where the data is stored upon writing the data to the temporary store element of the selected another memory device.

20. The apparatus of claim 19 wherein the processor is further configured to store the data back into the storage element upon reading back the data from the temporary store element of the selected another memory device.

21. The apparatus of claim 15 wherein the processor is configured to send a device address to the memory devices that determine address match in response to the sent device address to be selected.

22. A system comprising:

a plurality of memory devices connected in-series, each of the memory devices having a temporary store element and memory cells; and

an apparatus for communicating with the plurality of memory devices, the apparatus comprising a processor for

selecting a memory device of the plurality of memory devices,

writing data in the temporary store element of the selected memory device; and

reading back the data at a later time from the temporary store element of the selected memory device.

23. The system of claim 22 further comprising:

the processor being configured to free up space in the data storage where the second data is stored upon writing the second data to the temporary store element of the selected memory device.

24. The system of claim 23 further comprising:

the processor is configured to store the data back into the data storage upon reading back the data from the temporary store element of the selected memory device.

25. The system of claim 22 wherein the processor is configured to send a device address to the memory devices that determine address match in response to the sent device address to be selected.