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Network-On-Chip Environment and Method For Reduction of Latency

  • US 20080205432A1
  • Filed: 04/04/2006
  • Published: 08/28/2008
  • Est. Priority Date: 04/07/2005
  • Status: Abandoned Application
First Claim
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1. Integrated circuit comprising a plurality of processing modules (21, 23, M, S;

  • IP) and a network (NoC) arranged for coupling said processing modules (21, 23, M, S;

    IP),wherein the processing module (21, 23, M, S;

    IP) includes an associated network interface (NI) which is provided for transmitting data to the network (NoC) and for receiving data from the network (NoC);

    wherein data transmission between processing modules (21, 23, M, S;

    IP) is based on time division multiple access using time slots (S1-S20);

    wherein each network interface (NI) includes a slot table for storing an allocation of a time slot to a connection (C1-C4), andwherein multiple connections (C1-C4) are provided between a first processing module (21, M, IP) and a second processing module (23, S, IP) and a sharing of at least a part of time slots allocated to these multiple connections between the first and a second processing modules is provided.

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