Multi-Bus Structure For Optimizing System Performance Of a Serial Buffer

• US 20080205438A1
• Filed: 02/27/2007
• Published: 08/28/2008
• Est. Priority Date: 02/27/2007
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Wang, Chi-Lie, Juan, Steve, Chen, Ming-Shiung
• Granted Patent: US 8,094,677 B2
• Time in Patent Office: Days
• US Class Current: 370/465
• CPC Class Codes: H04L 12/4015 by scheduling the transmission of messages at the communication node
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/2441 relying on flow classification, e.g. using integrated services [IntServ]

Abstract

A serial buffer having a parser and multiple parallel processing paths is provided. The parser receives incoming packets, determines the type of each packet, and then routes each packet to a processing path that corresponds with the determined packet type. Packet types may include blocking priority packets (which implement bus slave operations), non-blocking priority packets (which access on-chip resources of the serial buffer) and data packets (which implement bus master operations). Because the different packet types are processed on parallel processing paths, the processing of one packet type does not interfere with the processing of other packet types. As a result, blocking conditions within the serial buffer are minimized.

Claims

1. A serial buffer comprising:

a parser configured to receive and separate incoming packets having a plurality of different packet types;

a first bus configured to receive packets of a first packet type from the parser;

a second bus configured to receive packets of a second packet type from the parser;

a first processing path coupled to the first bus and configured to process packets of the first packet type; and

a second processing path coupled to the second bus and configured to process packets of the second packet type, wherein the first processing path operates in parallel with the second processing path, such that processing of packets of the first packet type does not interfere with processing of packets of the second packet type.

2. The serial buffer of claim 1, wherein the first packet type has a first average processing time and the second packet type has a second average processing time, wherein the first average processing time is greater than the second average processing time.

3. The serial buffer of claim 1, wherein the first processing path comprises circuitry for implementing a bus slave operation.

4. The serial buffer of claim 3, wherein the circuitry for implementing the bus slave operation comprises:

a queue memory; and

a slave read block configured to retrieve data packets from the queue memory.

5. The serial buffer of claim 4, wherein the first processing path further comprises:

an output buffer configured to receive the data packets retrieved from the queue memory; and

an egress controller configured to route the data packets from the buffer to an outgoing bus of the serial buffer.

6. The serial buffer of claim 3, wherein the second processing path comprises circuitry for accessing on-chip registers of the serial buffer.

7. The serial buffer of claim 3, wherein the second processing path comprises circuitry for implementing a bus master operation.

8. The serial buffer of claim 1, wherein the first processing path comprises circuitry for implementing a bus master operation.

9. The serial buffer of claim 8, wherein the first processing path comprises a queue memory configured to receive packets of the first packet type from the first bus, and store these received packets of the first packet type.

10. The serial buffer of claim 9, wherein the first processing path further comprises a DMA engine configured to transfer packets out of the queue memory upon detecting that the queue memory exhibits a predetermined condition.

11. The serial buffer of claim 8, wherein the second processing path comprises circuitry for accessing on-chip registers of the serial buffer.

12. The serial buffer of claim 1, wherein the first processing path comprises circuitry for implementing memory accesses of a queue memory, and wherein the second processing path comprises circuitry for retrieving data from on-chip registers of the serial buffer.

13. The serial buffer of claim 12, further comprising an egress controller configured to route data accessed from the queue memory and the data retrieved from the on-chip registers to an outgoing bus of the serial buffer.

14. The serial buffer of claim 13, wherein the egress controller is configured to route the data retrieved from the on-chip registers and the data accessed from the queue memory based on assigned priorities.

15. The serial buffer of claim 12, further comprising:

a first output buffer configured to store the data accessed from the queue memory; and

a second output buffer configured to store the data retrieved from the on-chip registers.

16. The serial buffer of claim 1, wherein the second processing path comprises circuitry for accessing on-chip registers of the serial buffer.

17. The serial buffer of claim 1, further comprising:

a first input buffer configured to receive and store packets of the first packet type provided on the first bus; and

a second input buffer configured to receive and store packets of the second packet type provided on the second bus.

18. The serial buffer of claim 1, further comprising:

a third bus configured to receive packets of a third packet type from the parser;

a third processing path coupled to the third bus and configured to process packets of the third packet type, wherein the third processing path operates in parallel with the first and second processing paths, such that processing of packets of the third packet type does not interfere with processing of packets of the first packet type or the second packet type.

19. The serial buffer of claim 18, wherein the first processing path comprises circuitry for implementing a bus slave operation, the second processing path comprises circuitry for accessing on-chip registers of the serial buffer, and the third processing path comprises circuitry for implementing a bus master operation.

20. The serial buffer of claim 15, wherein the third processing path comprises a queue memory configured to receive packets of the third packet type from the third bus, and store these received packets of the third packet type.

21. The serial buffer of claim 19, wherein the third processing path comprises a DMA engine configured to transfer packets out of the queue memory upon detecting that the queue memory exhibits a predetermined condition.

22. The serial buffer of claim 19, wherein the circuitry for implementing the bus slave operation comprises a slave read block configured to retrieve data packets from the queue memory.

23. The serial buffer of claim 22, further comprising an output buffer configured to receive the data packets retrieved from the queue memory by the slave read block and the data packets transferred out of the queue memory by the DMA engine.

24. A method of operating a serial buffer comprising:

receiving an incoming packet stream having a plurality of different packet types;

separating packets of the incoming packet stream based on the packet types;

processing packets of a first packet type in a first processing path of the serial buffer; and

processing packets of a second packet type in a second processing path of the serial buffer, wherein processing packets of the first packet type does not interfere with processing packets of the second packet type.

25. The method of claim 24, further comprising processing packets of a third packet type in a third processing path of the serial buffer, wherein processing packets of the third packet type does not interfere with processing packets of the first packet type or the second packet type.