DSRC COMMUNICATION CIRCUIT AND DSRC COMMUNICATION METHOD

• US 20080205568A1
• Filed: 02/28/2007
• Published: 08/28/2008
• Est. Priority Date: 02/28/2007
• Status: Abandoned Application

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Oyama, Shigeki
• Application Number:
  US11/680,062
• Publication Number:
  US 20080205568A1
• Time in Patent Office: Days
• US Class Current: 375/365
• CPC Class Codes: H04B 7/2643 using time-division multiple access [TDMA] H04B7/2615, H04B7/2618 take precedence
• CPC Class Codes: H04W 56/00 Synchronisation arrangements

Abstract

A DSRC communication and DSRC communication method for preventing UW detection errors as a result of shifts in timings of received data and a UW detection window. A configuration is adopted where a frame timing generating section that receives a UW detection window timing signal of a receiving slot of the head of a frame, synchronizes frames, and counts up a first synchronization bit counter to generate a frame timing, and a UW detection window timing generating section that generates a timing signal for a UW detection window of a receiving slot of the head of the next frame using the generated frame timing as a reference, are provided, and the frame timing is maintained by taking the UW detection timing at receiving slot 100 of the head of the frame as frame synchronization timing 106, and loading and counting up a value of frame synchronization bit counter within the receiving circuit at frame synchronization timing 106.

Claims

1. A DSRC communication circuit comprising:

a frame timing generating section that receives a unique word detection window timing signal of a receiving slot of the head of a frame, synchronizes frames, and counts up a first synchronization bit counter to generate a frame timing; and

a unique word detection window timing generating section that generates a timing signal for a unique word detection window of a receiving slot of the head of the next frame using the generated frame timing as a reference.

3. The DSRC communication circuit according to claim 1, wherein the unique word detection window timing generating section generates the unique word detection window timing signal for detecting unique words at a plurality of slots configuring the frame according to the unique word detection window.

2. A DSRC communication circuit comprising:

a slot timing generating section that receives unique word detection window timing signals for all receiving slots, takes the unique word detection window timings as slot timings, and counts up a second synchronization bit counter to generate a slot timing; and

a unique word detection window timing generating section that generates a timing signal for a unique word detection window of a receiving slot which is other than the head of a frame using the generated slot timing as a reference.

4. A DSRC communication circuit comprising:

a unique word detection section that determines a unique word bit sequence through comparison with a bit sequence pattern of a unique word set in advance and generates a unique word detection signal; and

a receiving reference clock generating section that generates a receiving reference clock different from a demodulated receiving playback clock, wherein;

the unique word detection section carries out unique word detection using the receiving playback clock; and

the receiving reference clock generating section generates the receiving reference clock so as to match a timing of the unique word detection.

5. The DSRC communication circuit according to claim 4, further comprising a clock transferring section that temporarily stores received data in synchronization with the demodulated receiving playback clock, reads out the stored received data in synchronization with the receiving reference clock generated by the receiving reference clock generating section, and transfers a clock from the receiving playback clock to the receiving reference clock.

6. The DSRC communication circuit according to claim 5, wherein the UW detection section and/or the clock transferring section are provided for each one or plurality of modulation schemes.

7. The DSRC communication circuit according to claim 5, further comprising a selection section that selects whether switching of data of the modulation scheme for carrying out reception processing and receiving reference clock is set by the UW detection section or is set through mode setting.

8. A DSRC communication method comprising the steps of:

receiving a unique word detection window timing signal of a receiving slot of the head of a frame, synchronizing frames, and counting up a first synchronization bit counter to generate a frame timing; and

generating a timing signal for a unique word detection window of a receiving slot of the head of the next frame using the generated frame timing as a reference.

9. A DSRC communication method comprising the steps of:

receiving unique word detection window timing signals for all receiving slots, taking the unique word detection window timings as slot timings, and counting up a second synchronization bit counter to generate a slot timing; and

generating a timing signal for a unique word detection window of a receiving slot which is other than the head of the frame using the generated slot timing as a reference.

10. A DSRC communication method comprising the steps of:

determining a unique word bit sequence through comparison with a bit sequence pattern of a unique word set in advance and generating a unique word detection signal according to a receiving playback clock; and

generating a receiving reference clock signal different from a demodulated receiving playback clock so as to match a timing of the unique word detection.