TECHNIQUE FOR PATTERNING DIFFERENTLY STRESSED LAYERS FORMED ABOVE TRANSISTORS BY ENHANCED ETCH CONTROL STRATEGIES

• US 20080206905A1
• Filed: 10/08/2007
• Published: 08/28/2008
• Est. Priority Date: 02/28/2007
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Richter, Ralf, Salz, Heike, Mattick, Sylvio, Schaller, Matthias
• Granted Patent: US 7,883,629 B2
• Time in Patent Office: Days
• US Class Current: 438/16
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

During the patterning of stressed layers having different types of intrinsic stress, the effects of the deposition of a silicon dioxide based etch indicator material between the first and second dielectric layers may be significantly reduced by a controlled etch on the basis of optical measurement data indicating the etch rate and, thus, the performance of the respective etch process. In other cases, highly efficient etch indicator species may be incorporated into the stressed dielectric layers or may be formed on a surface portion thereof with reduced layer thickness, thereby providing an enhanced endpoint detection signal without creating the negative effects of silicon dioxide based indicator layers. In one illustrative embodiment, a stressed silicon, nitrogen and carbon-containing layer may be combined with a stressed silicon and nitrogen-containing layer, wherein the carbon species provides a prominent endpoint detection signal.

Claims

1. A method, comprising:

forming a first stress-inducing layer above a first transistor and a second transistor, said first and second transistors formed above a first substrate;

removing a portion of said first stress-inducing layer located above said second transistor;

forming a second stress-inducing layer on said first stress-inducing layer;

removing a portion of said second stress-inducing layer from above said first transistor on the basis of an etch process; and

controlling at least one parameter of said etch process on the basis of optical measurement data, said optical measurement data indicating an etch rate of said etch process.

2. The method of claim 1, further comprising controlling said etch process on the basis of measurement data indicating a layer thickness of said second stress-inducing layer.

3. The method of claim 1, wherein controlling said etch time comprises monitoring a thickness of said second layer to obtain said optical measurement data when etching said second stress-inducing layer.

4. The method of claim 3, wherein monitoring a thickness of said second layer comprises performing an interferometric measurement process.

5. The method of claim 1, further comprising forming a test structure based on said first and second stress-inducing layers above a second substrate and obtaining said optical measurement data by a scatterometry measurement process performed on said test structure.

6. The method of claim 5, wherein forming said test structure comprises patterning one of said first and second stress-inducing layers to form a grating pattern.

7. The method of claim 5, further comprising obtaining further optical measurement data from said test structure, said further optical measurement data indicating at least a thickness of said second stress-inducing layer prior to performing said etch process.

8. The method of claim 1, further comprising forming an etch stop layer above said first and second transistors prior to forming said first stress-inducing layer.

9. The method of claim 1, wherein said first and second stress-inducing layers are comprised of silicon nitride.

10. The method of claim 1, further comprising forming a dielectric material above said first and second transistors after said etch process, and forming contacts in said dielectric material using said first and second stress-inducing layers as an etch stop.

11. The method of claim 1, further comprising providing a specified atomic species in one of the first and second stress-inducing layers and controlling said etch process further on the basis of an optical signal obtained from said specified atomic species during said etch process.

12. The method of claim 11, wherein said atomic species comprises carbon.

13. The method of claim 1, wherein said at least one parameter comprises an etch time of said etch process.

14. The method of claim 1, wherein controlling at least one parameter comprises using a model of said etch process and estimating an updated value for said at least one parameter on the basis of said model and said optical measurement data.

15. A method, comprising:

forming a first stress-inducing layer above a first transistor and a second transistor, said first and second transistors formed above a substrate;

removing a portion of said first stress-inducing layer located above said second transistor;

forming a second stress-inducing layer on said first stress-inducing layer, said first and second stress-inducing layers differing in at least one type of atomic species; and

removing a portion of said second stress-inducing layer from above said first transistor on the basis of an etch process controlled on the basis of an optical signal obtained from said at least one type of differing atomic species.

16. The method of claim 15, wherein said first and second stress-inducing layers comprise silicon and nitrogen.

17. The method of claim 16, wherein said at least one type of differing atomic species is carbon.

18. The method of claim 17, wherein said second stress-inducing layer comprises said carbon and induces compressive stress.

19. The method of claim 17, wherein said first stress-inducing layer comprises said carbon and induces compressive stress.

20. A method, comprising:

providing a first stress-inducing layer above a substrate, said first stress-inducing layer covering a first transistor and exposing a second transistor;

providing an etch indicator layer on said first stress-inducing layer, said etch indicator layer having a thickness of approximately 5 nm or less;

forming a second stress-inducing layer on said etch indicator layer and above said second transistor; and

removing said second stress-inducing layer from above said first stress-inducing layer by an etch process controlled on the basis of a signal generated when said etch indicator layer is etched.

21. The method of claim 20, wherein said etch indicator layer is formed by a surface treatment of said first stress-inducing layer.

22. The method of claim 20, wherein said etch indicator layer is formed by at least one of chemical vapor deposition and physical vapor deposition.