Method for fabricating trench DMOS transistors and schottky elements

• US 20080206944A1
• Filed: 02/23/2007
• Published: 08/28/2008
• Est. Priority Date: 02/23/2007
• Status: Abandoned Application

• Current Assignee: Pan-Jit International Incorporated
• Original Assignee: Pan-Jit International Incorporated
• Inventors: Chuang, Chiao-Shun, Weng, Hung-Ta
• Application Number:
  US11/709,715
• Publication Number:
  US 20080206944A1
• Time in Patent Office: Days
• US Class Current: 438/237
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method uses simplified processes to complete the forming of the trench DMOS transistors and Schottky contacts. In the processes, only four masks, i.e. a trench pattern mask, a contact-hole pattern mask, a P+ contact pattern mask and a conductive-wire pattern mask, are applied to create desired trench DMOS transistors. In addition to the trench DMOS transistors, a Schottky contact is simultaneously formed at a junction between a conductive layer and a doped body region in the trench DMOS transistors without additional photolithography process.

Claims

1. A method for fabricating trench double diffused metal oxide semiconductor (DMOS) transistors and Schottky elements, the method comprising:

forming an epitaxial layer of a first type conductivity on a substrate of the first type conductivity;

forming a first oxide layer on the epitaxial layer;

defining trench patterns by using a first mask;

forming a body region of a second type conductivity within the epitaxial layer;

forming trenches through the body region based on the defined trench patterns;

growing a gate oxide layer for covering the body region;

filling the trenches with gate electrodes;

forming multiple doped regions of the first type conductivity within the body region between the trenches;

forming a passivation layer over the first oxide layer and covering the gate electrodes;

defining contact hole patterns by using a second mask;

forming contact holes through the passivation layer and the first oxide layer according to the defined contact hole patterns to expose portions of the body region;

defining contact region patterns by using a third mask;

forming contact regions of the second type conductivity within the exposed portions of the body region in the contact holes according to the defined contact region patterns;

defining conductive wire patterns by using a fourth mask; and

forming a conductive layer on the passivation layer, filling the contact holes and covering exposed portions of the epitaxial layer to form a Schottky contact at a junction between the conductive layer and the epitaxial layer.

2. The method as claimed in claim 1, wherein the first conductivity is an N type conductivity and the second conductivity is a P type conductivity.

3. The method as claimed in claim 1, the step of defining trench patterns further comprising:

coating a first photoresist layer on the first oxide layer; and

etching back the first oxide layer according to the defined trench patterns.

4. The method as claimed in claim 2, the step of defining trench patterns further comprising:

coating a first photoresist layer on the first oxide layer; and

etching back the first oxide layer according to the defined trench patterns.

5. The method as claimed in claim 2, after the forming of the body region, the method further comprising:

forming a second oxide layer on the first oxide layer and etching back to form sidewall oxide spacers abutting the first oxide layer.

6. The method as claimed in claim 2, the step of filling the trenches with gate electrodes further comprising:

depositing a polysilicon layer to fill the trenches and cover the first oxide layer; and

etching the polysilicon layer on the first oxide layer to retain the polysilicon layer within trenches as the gate electrodes.

7. The method as claimed in claim 1, wherein the first conductivity is a P type conductivity and the second conductivity is an N type conductivity.

8. The method as claimed in claim 7, the step of defining trench patterns further comprising:

coating a first photoresist layer on the first oxide layer; and

etching back the first oxide layer according to the defined trench patterns.

9. The method as claimed in claim 7, after the forming of the body region, the method further comprising:

forming a second oxide layer on the first oxide layer and etching back to form sidewall oxide spacers abutting the first oxide layer.

10. The method as claimed in claim 7, the step of filling the trenches with gate electrodes further comprising:

depositing a polysilicon layer to fill the trenches and cover the first oxide layer; and

etching the polysilicon layer on the first oxide layer to retain the polysilicon layer within trenches as the gate electrodes.