Method of fabricating a semiconductor device

• US 20080206985A1
• Filed: 07/25/2007
• Published: 08/28/2008
• Est. Priority Date: 02/28/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Hong, Chang-Ki, Yoon, Bo-un, Kwon, Byoung-ho, Shin, Sung-ho, Kim, Chae-Iyoung
• Granted Patent: US 7,781,330 B2
• Time in Patent Office: Days
• US Class Current: 438/637
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/7688 by deposition over sacrificial masking layer, e.g. lift-off lift-off per se H01L21/0272
• CPC Class Codes: Y10S 438/947 Subphotolithographic processing

Abstract

Methods of fabricating a semiconductor device is provided. The methods include forming an interlayer insulating layer on a semiconductor substrate having a first region and a second region. First contact plugs may be formed on a portion of the second region to fill a plurality of first contact holes. A plurality of first contact mask layers and a plurality of first dummy mask layers may be formed on the interlayer insulating layer. The first contact mask layers may be formed in the first region. The first dummy mask layers may be formed in the second region. A plurality of second contact mask layers may be formed between two adjacent first contact mask layers. A plurality of second dummy mask layers may be formed between two adjacent first dummy mask layers. The interlayer insulating layer may be etched using the first contact mask layers and the second contact mask layers as etch stop layers to form a plurality of second contact holes through the interlayer insulating layer formed in the first region.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming an interlayer insulating layer on a semiconductor substrate including a first region and a second region;

forming first contact plugs on a portion of the second region to fill a plurality of first contact holes formed through the interlayer insulating layer;

forming a plurality of first contact mask layers and a plurality of first dummy mask layers on the interlayer insulating layer, wherein the plurality of first contact mask layers are formed in the first region and the plurality of first dummy mask layers are formed in the second region;

forming a plurality of second contact mask layers and a plurality of second dummy mask layers, wherein each of the plurality of second contact mask layers are formed between two of the plurality of first contact mask layers that are adjacent and each of the second dummy mask layers are formed between two of the plurality of first dummy mask layers that are adjacent; and

forming a plurality of second contact holes through the interlayer insulating layer formed in the first region by etching the interlayer insulating layer using the plurality of first contact mask layers and the plurality of second contact mask layers as etch protection layers.

2. The method of claim 1, wherein the plurality of second contact mask layers and the plurality of second dummy mask layers are formed on the interlayer insulating layer.

3. The method of claim 2, wherein the plurality of first contact mask layers and the plurality of first dummy mask layers are formed simultaneously.

4. The method of claim 3, wherein forming the plurality of first contact plugs, the plurality of first contact mask layers and the plurality of first dummy mask layers includes patterning a first conductive layer.

5. The method of claim 4, wherein the first conductive layer includes polysilicon.

6. The method of claim 2, wherein the plurality of first contact mask layers are formed having substantially the same width and at substantially the same interval as the plurality of first dummy mask layers.

7. The method of claim 2, wherein forming the plurality of second contact mask layers and the plurality of second dummy mask layers includes:

forming a mold layer on the interlayer insulating layer to define a plurality of recesses between each of the plurality of first contact mask layers that are adjacent and between each of the plurality of first dummy mask layers that are adjacent; and

forming a second conductive layer in the plurality of recesses.

8. The method of claim 7, further comprising forming grooves by etching the interlayer insulating layer exposed by the plurality of first contact plugs, the plurality of first contact mask layers and the plurality of first dummy mask layers to a desired thickness, prior to forming the mold layer.

9. The method of claim 7, wherein a thickness of the mold layer determines a width of each of the plurality of second contact holes.

10. The method of claim 7, wherein the mold layer and the interlayer insulating layer each include an oxide layer.

11. The method of claim 7, wherein the second conductive layer includes polysilicon.

12. The method of claim 2, further comprising filling the plurality of second contact holes with a plurality of second contact plugs, after forming the plurality of second contact holes.

13. The method of claim 12, wherein the plurality of first contact plugs, the plurality of second contact plugs, the plurality of first contact mask layers, the plurality of second contact mask layers, the plurality of first dummy mask layers and the plurality of second dummy mask layers are formed of the same material.

14. The method of claim 12, wherein the plurality of first contact plugs are formed having a larger width than the plurality of second contact plugs.

15. The method of claim 12, wherein forming of the second contact plugs includes:

forming a third conductive layer on the semiconductor substrate filling the plurality of second contact holes; and

planarizing the third conductive layer.

16. The method of claim 15, wherein planarizing the third conductive layer includes simultaneously removing the plurality of first contact mask layers, the plurality of first dummy mask layers, the plurality of second contact mask layers and the plurality of second dummy mask layers.

17. The method of claim 15, wherein the third conductive layer includes polysilicon.

18. The method of claim 2, wherein the first region is a cell region, and the second region is a peripheral circuit region.

19. The method of claim 1, further comprising:

forming a mold layer on the interlayer insulating layer to define a plurality of recesses between each of the plurality of first contact mask layers that are adjacent and between each of the plurality of first dummy mask layers that are adjacent; and

forming a plurality of second contact plugs filling the second contact holes,

wherein the first region is a cell region and the second region is a peripheral circuit region, and

the plurality of second contact mask layers and the plurality of second dummy mask layers are formed in the plurality of recesses.

20. The method of claim 19, wherein the plurality of first contact mask layers are formed having the same width and at substantially the same interval as the plurality of first dummy mask layers.

21. The method of claim 19, wherein the plurality of first contact plugs, the plurality of second contact plugs, the plurality of first contact mask layers, the plurality of second contact mask layers, the plurality of first dummy mask layers and the plurality of second dummy mask layers are formed of the same material.

22. The method of claim 19, wherein the plurality of first contact plugs are formed having a larger width than the plurality of second contact plugs.