Methods and systems for optimizing placement on a clock signal distribution network

• US 20080209038A1
• Filed: 02/23/2007
• Published: 08/28/2008
• Est. Priority Date: 02/23/2007
• Status: Abandoned Application

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Raza Microelectronics Inc (Broadcom, Inc.)
• Inventors: Tufano, Andrew J.
• Application Number:
  US11/710,249
• Publication Number:
  US 20080209038A1
• Time in Patent Office: Days
• US Class Current: 709/225
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/396 Clock trees

Abstract

Methods for optimizing an initial placement a number of features over a clock signal distribution network on an integrated circuit (IC), wherein the plurality of features includes a plurality of registers and a corresponding plurality of local drivers are presented, the methods including: characterizing the number of features by a number of register groupings, the number of register groupings defined by similarity of corresponding local drivers, wherein each of the number of register groupings is physically delimited by a defined region on the clock signal distribution network in the initial placement; and iteratively moving the number of register groupings in accordance with a number of exception based rules over an increasingly widening area of comparison to create an optimized placement of the number of features.

Claims

1. A method for optimizing an initial placement a plurality of features over a clock signal distribution network on an integrated circuit (IC), wherein the plurality of features includes a plurality of registers and a corresponding plurality of local drivers, the method comprising:

characterizing the plurality of features by a plurality of register groupings, the plurality of register groupings defined by similarity of corresponding local drivers, wherein each of the plurality of register groupings is physically delimited by a defined region on the clock signal distribution network in the initial placement; and

iteratively moving the plurality of register groupings in accordance with a plurality of exception based rules over an increasingly widening area of comparison to create an optimized placement of the plurality of features.

2. The method of claim 1 further comprising:

placing the plurality of register groupings on the clock signal distribution network in accordance with the iteratively moving the plurality of register groupings;

placing the corresponding plurality of local drivers on a clock row in accordance with the placing the plurality of register groupings;

placing a plurality of clock drivers on a spine region, the plurality of clock drivers configured to provide the corresponding plurality of drivers a common clock signal; and

placing a plurality of routes, the plurality of routes configured to connect the plurality of clock drivers with the corresponding plurality of local drivers and the plurality of corresponding local drivers with the plurality of register groupings.

3. The method of claim 1 further comprising;

generating a quality report for determining a plurality of performance characteristics corresponding with the optimized placement.

4. The method of claim 1 wherein the increasingly widening area of comparison comprises:

a first level of comparison, wherein the first level of comparison requires that the plurality of exception based rules are strictly enforced, and wherein the plurality of exception based rules are iteratively and repeatedly applied across all defined regions until none of the plurality of exception based rules are enforceable, the first level of comparison corresponding with a first plurality of comparison regions, the first plurality of comparison regions located immediately adjacent with the defined region;

a second level of comparison, wherein the second level of comparison requires that the plurality of exception based rules are strictly enforced, and wherein the plurality of exception based rules are iteratively and repeatedly applied across all defined regions until none of the plurality of exception based rules are enforceable, the second level of comparison corresponding with a second plurality of comparison regions and the first level of comparison regions, the second plurality of comparison regions located immediate adjacent with the first plurality of comparison regions; and

a third level of comparison, wherein the third level of comparison requires that the plurality of exception based rules are selectively enforced, and wherein the plurality of exception based rules are iteratively and repeatedly applied across all defined regions until none of the plurality of exception based rules are enforceable, the third level of comparison corresponding with a third plurality of comparison regions, the second plurality of comparison regions, and the first plurality of comparison regions, the third plurality of comparison regions located immediate adjacent with the second plurality of comparison regions.

5. The method of claim 4 wherein the plurality of exception based rules is selected from the group consisting of:

a minimum bit width exception rule, a local driver exception rule, and a defined region utilization exception rule.

6. The method of claim 5 wherein the enforcing the minimum bit width exception rule comprises:

finding a minimum bit width violator in a relevant comparison region, wherein the relevant comparison region alternately corresponds with the first level of comparison, the second level of comparison, and the third level of comparison;

moving the minimum bit width violator into the defined region, wherein the minimum bit width violator is moved to a location proximal with a first local driver, the first local driver having the highest fan out;

if the moving creates a new violation,

alternatively swapping the minimum bit width violator into the defined region; and

if the swapping creates the new violation,

alternatively ignoring the minimum bit width violator.

7. The method of claim 6 wherein the enforcing the minimum bit width exception rule further comprises:

finding the minimum bit width violator in the defined region;

if the minimum bit width violator is located within a defined distance from a second local driver and the relevant comparison includes an area sufficiently sized to receive the minimum bit width violator,

moving the minimum bit width violator into the relevant comparison region wherein the minimum bit width violator is moved to a location proximal with the second local driver;

if the moving creates the new violation,

alternatively swapping the minimum bit width violator into the relevant comparison region; and

if the swapping creates the new violation,

alternatively ignoring the minimum bit width violator.

8. The method of claim 7 wherein the enforcing the minimum bit width exception rule further comprises:

finding the minimum bit width violator in a relevant comparison region, wherein the relevant comparison region alternately corresponds with the first level of comparison, the second level of comparison, and the third level of comparison;

moving the minimum bit width violator into the defined region, wherein the minimum bit width violator is located proximal with a third local driver, the third local driver having a second highest fan out;

if the moving creates the new violation,

alternatively swapping the minimum bit width violator into the defined region; and

if the swapping creates the new violation,

alternatively ignoring the minimum bit width violator.

9. The method of claim 5 wherein enforcing the local driver exception rule comprises:

finding a local driver violator in the defined region;

moving the local driver violator into a relevant comparison region, wherein the relevant comparison region alternately corresponds with the first level of comparison, the second level of comparison, and the third level of comparison;

if the moving creates the new violation,

alternatively swapping the local driver violator into the relevant comparison region; and

if a total number of local drivers does not decrease with the swapping,

alternatively ignoring the local driver violator

10. The method of claim 5 wherein enforcing the defined region utilization exception rule comprises:

finding a defined region utilization violator in the defined region;

moving the defined region utilization violator into a relevant comparison region, the relevant comparison region having a subset of registers of a same enable net group, wherein the relevant comparison region alternately corresponds with the first level of comparison, the second level of comparison, and the third level of comparison;

if the moving creates the new violation or if the relevant comparison region lacks the same enable net group;

alternatively moving the defined region utilization violator into the relevant comparison region; and

if the moving creates the new violation,

alternatively ignoring the defined region utilization violator.

11. The method of claim 1 wherein clock signal distribution network is MIPS compliant.

12. The method of claim 1 wherein the clock signal distribution network is configured as a clock mesh synthesis.

13. The method of claim 1 wherein the plurality of features is selected from the group consisting of:

an AND gate, a buffer, an inverter, and a register.

14. The method of claim 1 wherein the iteratively moving continues until an iteration condition is reached, wherein the iteration condition is selected from the group consisting of:

an all exceptions cleared condition for an area of comparison, an all exceptions processed condition for the area of comparison, and a maximum number of iterations condition for the area of comparison.

15. The method of claim 1 wherein the corresponding plurality of local drivers includes at least one unqualified driver and at least one qualified driver.

16. A system for optimizing an initial placement of a plurality of features over a clock signal distribution network on an integrated circuit (IC) layout, wherein the plurality of features includes a plurality of registers and a corresponding plurality of local drivers, the system comprising:

a register transfer language (RTL) module for creating a plurality of code expressions in an RTL;

a synthesis module for mapping the RTL to a plurality of logic circuits based on a first output from the RTL module;

a floor plan module for determining a first physical space requirement for the clock signal distribution network based on a second output from the synthesis module;

a clock grid design (CGD) floor plan module for defining a set of physical dimensions corresponding with the clock signal distribution network based on a third output from the floor plan module, the CGD floor plan module further configured for determining a second physical space requirement for the plurality of local drivers corresponding with the plurality of logic circuits;

a placement module for creating the initial placement of the plurality of features,

a CGD placement module for optimizing the initial placement, the CGD configured to,

group the plurality of registers in accordance with a plurality of iteratively applied exception based rules,

place the plurality of local drivers, and

place a plurality of clock drivers; and

a route module for establishing a plurality of connections between the plurality of registers, the plurality of local drivers, and the plurality of c wherein an optimized placement is output.

17. The system of claim 16 further comprising:

a CGD analysis module for determining an efficiency of an optimized placement.

18. The system of claim 17 wherein the CGD analysis module is configured to provide Simulation Program for Integrated Circuits Emphasis (SPICE) support.

19. A method for optimizing an initial placement a plurality of features over a clock signal distribution network on an integrated circuit (IC), wherein the plurality of features includes a plurality of registers and a corresponding plurality of local drivers, the method comprising:

means for characterizing the plurality of features by a plurality of register groupings, the plurality of register groupings defined by similarity of corresponding local drivers, wherein each of the plurality of register groupings is physically delimited by a defined region on the clock signal distribution network in the initial placement; and

means for iteratively moving the plurality of register groupings in accordance with a plurality of exception based rules over an increasingly widening area of comparison to create an optimized placement of the plurality of features.

20. The method of claim 19 further comprising:

means for placing the plurality of register groupings on the clock signal distribution network in accordance with the means for iteratively moving the plurality of register groupings;

means for placing the corresponding plurality of local drivers on a clock row in accordance with the placing the plurality of register groupings;

means for placing a plurality of clock drivers on a spine region, the plurality of clock drivers configured to provide the corresponding plurality of drivers a common clock signal; and

means for placing a plurality of routes, the plurality of routes configured to connect the plurality of clock drivers with the corresponding plurality of local drivers and the plurality of corresponding local drivers with the plurality of register groupings.

21. The method of claim 19 further comprising:

means for generating a quality report for determining a plurality of performance characteristics corresponding with the optimized placement.