Methods and systems for optimizing placement on a clock signal distribution network
First Claim
1. A method for optimizing an initial placement a plurality of features over a clock signal distribution network on an integrated circuit (IC), wherein the plurality of features includes a plurality of registers and a corresponding plurality of local drivers, the method comprising:
- characterizing the plurality of features by a plurality of register groupings, the plurality of register groupings defined by similarity of corresponding local drivers, wherein each of the plurality of register groupings is physically delimited by a defined region on the clock signal distribution network in the initial placement; and
iteratively moving the plurality of register groupings in accordance with a plurality of exception based rules over an increasingly widening area of comparison to create an optimized placement of the plurality of features.
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Accused Products
Abstract
Methods for optimizing an initial placement a number of features over a clock signal distribution network on an integrated circuit (IC), wherein the plurality of features includes a plurality of registers and a corresponding plurality of local drivers are presented, the methods including: characterizing the number of features by a number of register groupings, the number of register groupings defined by similarity of corresponding local drivers, wherein each of the number of register groupings is physically delimited by a defined region on the clock signal distribution network in the initial placement; and iteratively moving the number of register groupings in accordance with a number of exception based rules over an increasingly widening area of comparison to create an optimized placement of the number of features.
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Citations
21 Claims
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1. A method for optimizing an initial placement a plurality of features over a clock signal distribution network on an integrated circuit (IC), wherein the plurality of features includes a plurality of registers and a corresponding plurality of local drivers, the method comprising:
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characterizing the plurality of features by a plurality of register groupings, the plurality of register groupings defined by similarity of corresponding local drivers, wherein each of the plurality of register groupings is physically delimited by a defined region on the clock signal distribution network in the initial placement; and iteratively moving the plurality of register groupings in accordance with a plurality of exception based rules over an increasingly widening area of comparison to create an optimized placement of the plurality of features. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A system for optimizing an initial placement of a plurality of features over a clock signal distribution network on an integrated circuit (IC) layout, wherein the plurality of features includes a plurality of registers and a corresponding plurality of local drivers, the system comprising:
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a register transfer language (RTL) module for creating a plurality of code expressions in an RTL; a synthesis module for mapping the RTL to a plurality of logic circuits based on a first output from the RTL module; a floor plan module for determining a first physical space requirement for the clock signal distribution network based on a second output from the synthesis module; a clock grid design (CGD) floor plan module for defining a set of physical dimensions corresponding with the clock signal distribution network based on a third output from the floor plan module, the CGD floor plan module further configured for determining a second physical space requirement for the plurality of local drivers corresponding with the plurality of logic circuits; a placement module for creating the initial placement of the plurality of features, a CGD placement module for optimizing the initial placement, the CGD configured to, group the plurality of registers in accordance with a plurality of iteratively applied exception based rules, place the plurality of local drivers, and place a plurality of clock drivers; and a route module for establishing a plurality of connections between the plurality of registers, the plurality of local drivers, and the plurality of c wherein an optimized placement is output. - View Dependent Claims (17, 18)
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19. A method for optimizing an initial placement a plurality of features over a clock signal distribution network on an integrated circuit (IC), wherein the plurality of features includes a plurality of registers and a corresponding plurality of local drivers, the method comprising:
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means for characterizing the plurality of features by a plurality of register groupings, the plurality of register groupings defined by similarity of corresponding local drivers, wherein each of the plurality of register groupings is physically delimited by a defined region on the clock signal distribution network in the initial placement; and means for iteratively moving the plurality of register groupings in accordance with a plurality of exception based rules over an increasingly widening area of comparison to create an optimized placement of the plurality of features. - View Dependent Claims (20, 21)
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Specification