Hardware-Based Concurrent Direct Memory Access (DMA) Engines On Serial Rapid Input/Output SRIO Interface

• US 20080209084A1
• Filed: 02/27/2007
• Published: 08/28/2008
• Est. Priority Date: 02/27/2007
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Tezcan, Bertan, Wang, Chi-Lie
• Granted Patent: US 8,516,163 B2
• Time in Patent Office: Days
• US Class Current: 710/22
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A serial buffer includes queues configured to store data packets received from a host. A direct memory access (DMA) engine receives data packets from the highest priority queue having a water level that reaches a corresponding watermark. The DMA engine is configured in response to a DMA register set, which is selected from a plurality of DMA register sets. The DMA register set used to configure the DMA engine can be selected in response to information in the header of the read data packet, or in response to the queue from which the data packet is read. Each DMA register set defines a corresponding buffer in system memory, to which the data packet is transferred. Each DMA register set also defines whether the corresponding buffer is accessed in a wrap mode or a stop mode, and whether doorbell signals are generated in response to transfers to the last address in the corresponding buffer.

Claims

1. A serial buffer comprising:

a plurality of queues configured to store data packets received from a host;

a direct memory access (DMA) engine coupled to receive data packets read from the queues; and

a plurality of DMA register sets, wherein each of the DMA register sets is configured to store parameters that define a corresponding DMA channel of the DMA engine; and

circuitry for selecting one of the DMA register sets to configure the DMA engine, thereby enabling the DMA engine to transfer the received data packets to a system memory using the corresponding DMA channel.

2. The serial buffer of claim 1, wherein each of the DMA register sets include a start address register configured to store a start address and a stop address register configured to store a stop address, wherein the start address and the stop address define a unique buffer within the system memory.

3. The serial buffer of claim 2, wherein each of the DMA register sets include a next address register configured to load the start address from the start address register.

4. The serial buffer of claim 3, further comprising means for incrementing the next address register of the selected one of the DMA register sets when the DMA engine implements a transfer to the system memory.

5. The serial buffer of claim 4, wherein the DMA engine is configured to access the system memory in response to the contents of the next address register of the selected one of the DMA register sets.

6. The serial buffer of claim 3, further comprising a comparator having inputs coupled to the stop address register and the next address register of the selected one of the DMA register sets.

7. The serial buffer of claim 2, wherein each of the DMA register sets include a wrap/stop register configured to store a wrap_stop identifier that indicates whether or not the buffer is accessed in a wrap-around manner.

8. The serial buffer of claim 2, wherein each of the DMA register sets include a wrap/stop doorbell register configured to store a wrap_stop doorbell enable signal that indicates whether or not the serial buffer transmits a doorbell to the host when the DMA engine implements a transfer to an associated stop address.

9. The serial buffer of claim 1, wherein the circuitry for selecting one of the DMA register sets operates in response to which of the queues provides the data packets to the DMA engine.

10. The serial buffer of claim 9, wherein the circuitry for selecting one of the DMA register sets operates in response to information included in the data packets received by the DMA engine.

11. The serial buffer of claim 1, wherein the circuitry for selecting one of the DMA register sets operates in response to information included in the data packets received by the DMA engine.

12. The serial buffer of claim 1, further comprising:

a plurality of water level indicators, each associated with a corresponding one of the queues;

a plurality of watermark indicators, each associated with a corresponding one of the queues; and

a comparator coupled to receive the water level indicators and the watermark indicators, and in response, activate a control signal when a water level indicator associated with a queue reaches a watermark indicator associated with the queue.

13. The serial buffer of claim 12, wherein each of the queues has an assigned priority, further comprising logic for identifying a highest priority queue having an associated water level indicator that has reached the associated watermark indicator.

14. The serial buffer of claim 1, further comprising a plurality of queue channel select registers, each associated with a corresponding one of the queues, and each configured to store a channel select value that defines a DMA register set associated with the corresponding one of the queues.

15. A method of performing a DMA transfer in a serial buffer, comprising:

retrieving a first data packet from a first queue of the serial buffer;

selecting a first DMA register set in response to information included in a header of the first data packet; and

configuring a DMA engine to transfer the first data packet in response to the first DMA register set.

16. The method of claim 15, further comprising:

assigning priorities to the first queue and other queues of the serial buffer; and

identifying the first queue as the highest priority queue having an associated water level that reaches an associated watermark prior to retrieving the first data packet from the first queue.

17. The method of claim 15, further comprising:

retrieving a second data packet from a second queue of the serial buffer;

selecting a second DMA register set corresponding with the second queue of the serial buffer; and

configuring the DMA engine to transfer the second data packet in response to the second DMA register set.

18. The method of claim 15, further comprising defining a first buffer to receive the first data packet in response to the first DMA register set.

19. The method of claim 18, further comprising using the first DMA register set to define the transfer of the first data packet if the first data packet overruns the first buffer.

20. The method of claim 19, further comprising generating a doorbell command if the first data packet overruns the first buffer.

21. The method claim 19, further comprising:

retrieving a second data packet from the first queue of the serial buffer;

selecting a second DMA register set in response to information included in a header of the second data packet; and

configuring the DMA engine to transfer the second data packet in response to the second DMA register set.

22. The method of claim 21, further comprising:

defining a first buffer to receive the first data packet in response to the first DMA register set;

stopping transfer of the first data packet if the first data packet fills the first buffer;

defining a second buffer to receive the second data packet in response to the second DMA register set; and

transferring the second data packet to the second buffer while transfer of the first data packet is stopped.

23. A method of performing a DMA transfer in a serial buffer, comprising:

retrieving a first data packet from a first queue of the serial buffer;

selecting a first DMA register set corresponding with the first queue of the serial buffer;

configuring the DMA engine to transfer the first data packet in response to the first DMA register set;

retrieving a second data packet from a second queue of the serial buffer;

selecting a second DMA register set corresponding with the second queue of the serial buffer; and

configuring the DMA engine to transfer the second data packet in response to the second DMA register set.

24. The method of claim 23, further comprising:

defining a first buffer to receive the first data packet in response to the first DMA register set;

stopping transfer of the first data packet if the first data packet fills the first buffer;

defining a second buffer to receive the second data packet in response to the second DMA register set; and

transferring the second data packet to the second buffer while transfer of the first data packet is stopped.

25. The method of claim 24, further comprising assigning priorities to the first queue and the second queue, wherein the priority of the second queue is higher than the priority of the first queue.