Multi-Processor Flash Memory Storage Device and Management System
First Claim
Patent Images
1. A data storage device comprising:
- a host controller interface;
a plurality of microprocessor units each having a portion of random access memory (RAM) dedicated thereto;
a plurality of memory device configurations each having dedicated bus connections to individual ones or multiples of the microprocessor units; and
a dataflow controller accessible to the host controller interface for managing access to the device configurations.
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Abstract
A data storage device has a host controller interface, a plurality of microprocessor units each having a portion of random access memory (RAM) dedicated thereto, a plurality of Flash device configurations each having dedicated bus connections to individual ones or multiples of the microprocessor units, and a dataflow controller accessible to the host controller interface for managing access to the Flash device configurations.
111 Citations
15 Claims
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1. A data storage device comprising:
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a host controller interface; a plurality of microprocessor units each having a portion of random access memory (RAM) dedicated thereto; a plurality of memory device configurations each having dedicated bus connections to individual ones or multiples of the microprocessor units; and a dataflow controller accessible to the host controller interface for managing access to the device configurations. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A Flash channel configured for data storage, comprising:
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a coupled configuration of one or more Flash memory devices; a bus structure connected to the Flash device configuration, the bus including an address line, a data line, and a control line; and one or more microprocessor units also connected to the bus structure, and having a portion of RAM dedicated thereto. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A Flash channel configured for data storage, comprising:
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two or more Flash device configurations comprising one or more Flash memory devices; two or more bus structures connected to each Flash device configuration, the bus structures each including an address line, a data line, and a control line; and a single microprocessor unit also connected to the bus structures, the microprocessor unit having a portion of RAM dedicated thereto.
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Specification