Translation Data Prefetch in an IOMMU

• US 20080209130A1
• Filed: 04/30/2008
• Published: 08/28/2008
• Est. Priority Date: 08/12/2005
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Kegel, Andrew G., Hummel, Mark D., Boleyn, Erich S.
• Granted Patent: US 7,793,067 B2
• Time in Patent Office: Days
• US Class Current: 711/135
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 12/145 the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/654 Look-ahead translation

Abstract

In an embodiment, a system memory stores a set of input/output (I/O) translation tables. One or more I/O devices initiate direct memory access (DMA) requests including virtual addresses. An I/O memory management unit (IOMMU) is coupled to the I/O devices and the system memory, wherein the IOMMU is configured to translate the virtual addresses in the DMA requests to physical addresses to access the system memory according to an I/O translation mechanism implemented by the IOMMU. The IOMMU comprises one or more caches, and is configured to read translation data from the I/O translation tables responsive to a prefetch command that specifies a first virtual address. The reads are responsive to the first virtual address and the I/O translation mechanism, and the IOMMU is configured to store data in the caches responsive to the read translation data.

Claims

1. A method comprising:

receiving a prefetch command in an input/output (I/O) memory management unit (IOMMU), wherein the prefetch command specifies a virtual address;

reading translation data from one or more I/O translation tables in system memory of a system that includes the IOMMU, wherein the reading is responsive to the virtual address and to an I/O translation mechanism implemented by the IOMMU to translate virtual addresses in direct memory access (DMA) requests transmitted by one or more I/O devices; and

storing data in one or more caches of the IOMMU responsive to the reading.

2. The method as recited in claim 1 wherein the one or more caches comprise at least a first cache configured to store I/O translation table entries read from the one or more of I/O translation tables, and wherein the storing comprises storing the read translation entries in the first cache.

3. The method as recited in claim 1 wherein the one or more caches comprise a translation lookaside buffer (TLB) configured to store portions of virtual addresses and corresponding portions of physical addresses determined by translating the virtual addresses in the I/O translation mechanism according to data read from the one or more I/O translation tables, wherein the storing comprises storing the portion of the virtual address from the prefetch command and the resulting physical address in the TLB.

4. The method as recited in claim 1 further comprising the IOMMU indicating success of the prefetch command independent of a result of translating the virtual address.

5. The method as recited in claim 4 wherein the IOMMU indicating success occurs prior to reading the translation data.

6. The method as recited in claim 1 wherein the prefetch command further specifies a device identifier that is assigned to a first I/O device of the one or more I/O devices, and wherein the method further comprises selecting the one or more I/O translation tables from multiple sets of I/O translation tables responsive to the device identifier.

7. The method as recited in claim 1 further comprising:

receiving a second prefetch command in the IOMMU, wherein the second prefetch command specifies a second virtual address;

determining that there is not an available cache entry in the one or more caches to store data corresponding to the second virtual address; and

not reading the translation data corresponding to the second virtual address responsive to the determining.

8. The method as recited in claim 1 further comprising:

determining that there is not an available cache entry in the one or more caches to store data corresponding to the virtual address; and

evicting data from the one or more caches to free a cache entry or entries to store the data corresponding to the virtual address.

9. The method as recited in claim 1 further comprising marking the stored data as first to be evicted from the cache if eviction is signalled.

10. The method as recited in claim 1 further comprising:

receiving a second prefetch command in the IOMMU, wherein the second prefetch command specifies a second virtual address;

detecting a hit corresponding to the second virtual address in the one or more caches; and

not reading the translation data corresponding to the second virtual address responsive to the detecting.

11. An input/output (I/O) memory management unit (IOMMU) comprising:

one or more caches; and

a table walk unit configured coupled to the one or more caches and configured, in response to a prefetch command that specifies a virtual address, to read translation data from one or more I/O translation tables stored in a system memory of a system that includes the IOMMU, wherein the reads are responsive to the virtual address and an I/O translation mechanism implemented by the IOMMU for direct memory access (DMA) requests transmitted by one or more I/O devices in the system, and wherein the table walk unit is configured to store data in the one or more caches responsive to the read translation data.

12. The IOMMU as recited in claim 11 wherein the one or more caches comprise at least a first cache configured to store I/O translation table entries read from the one or more I/O translation tables, and wherein the table walk unit is configured to store the read translation entries in the first cache.

13. The IOMMU as recited in claim 11 wherein the one or more caches comprise a translation lookaside buffer (TLB) configured to store portions of virtual addresses and corresponding portions of physical addresses determined by translating the virtual addresses in the I/O translation mechanism according to data read from the one or more I/O translation tables, wherein the table walk unit is configured to store the portion of the virtual address from the prefetch command and the resulting physical address in the TLB.

14. The IOMMU as recited in claim 11 wherein the prefetch command further specifies a device identifier that is assigned to a first I/O device of the one or more I/O devices, and wherein the IOMMU is configured to select the one or more I/O translation tables from multiple sets of I/O translation tables responsive to the device identifier.

15. The IOMMU as recited in claim 11 further comprising a control unit coupled to the one or more caches, wherein the control unit is configured to determining whether or not there is an available cache entry in the one or more caches to store data corresponding to the virtual address, and wherein the control unit is configured to prevent the reading of the translation data responsive to determining that there is not an available cache entry.

16. The IOMMU as recited in claim 11 further comprising a control unit coupled to the one or more caches, wherein the control unit is configured to determining whether or not there is an available cache entry in the one or more caches to store data corresponding to the virtual address, and wherein the control unit is configured to evict data from the one or more caches to free a cache entry or entries to store the data corresponding to the virtual address.

17. The IOMMU as recited in claim 11 further comprising a control unit coupled to the one or more caches, wherein the control unit is configured to detect a hit corresponding to the virtual address in the one or more caches, and wherein the control unit is configured to prevent the reading of the translation data responsive to detecting the hit.

18. The IOMMU as recited in claim 11 wherein the prefetch command comprises an invalidate indication, and wherein the control unit is configured to detect a hit in the one or more caches for the virtual address and is configured to invalidate the hitting entry in the one or more caches responsive to the invalidate indication indicating invalidate.

19. A system comprising:

a system memory configured to store one or more input/output (I/O) translation tables;

one or more I/O devices configured to initiate direct memory access (DMA) requests including virtual addresses; and

an I/O memory management unit (IOMMU) coupled to the one or more I/O devices and the system memory, wherein the IOMMU is configured to translate the virtual addresses in the DMA requests to physical addresses to access the system memory according to an I/O translation mechanism implemented by the IOMMU and responsive to the I/O translation tables, wherein the IOMMU comprises one or more caches, and wherein the IOMMU, responsive to a prefetch command that specifies a first virtual address, is configured to read translation data from the I/O translation tables, wherein the reads are responsive to the first virtual address and the I/O translation mechanism, and wherein the IOMMU is configured to store data in the one or more caches responsive to the read translation data.

20. The system as recited in claim 19 further comprising a processor configured to transmit the prefetch command.