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METHOD AND APPARATUS FOR ANALYZING CIRCUIT MODEL BY REDUCTION AND COMPUTER PROGRAM PRODUCT FOR ANALYZING THE CIRCUIT MODEL

  • US 20080209366A1
  • Filed: 02/07/2008
  • Published: 08/28/2008
  • Est. Priority Date: 02/27/2007
  • Status: Active Grant
First Claim
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1. A method of analyzing a circuit model by reduction, the method comprising:

  • inputting information about the circuit model, the information comprising a circuit net list with independent current sources and a node state information of each of a plurality of nodes in the circuit model;

    selecting one of the nodes to be removed;

    removing the selected node and generating a reduced circuit; and

    post-processing a reduced circuit net list from intermediate data of the reduced circuit.

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