METHOD AND APPARATUS FOR ANALYZING CIRCUIT MODEL BY REDUCTION AND COMPUTER PROGRAM PRODUCT FOR ANALYZING THE CIRCUIT MODEL

• US 20080209366A1
• Filed: 02/07/2008
• Published: 08/28/2008
• Est. Priority Date: 02/27/2007
• Status: Active Grant

• Current Assignee: Postech Academy-Industry Foundation
• Original Assignee: Postech Academy-Industry Foundation
• Inventors: Che, Hong Bo, Kim, Young Hwan
• Granted Patent: US 7,987,439 B2
• Time in Patent Office: Days
• US Class Current: 716/4
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

Provided are a method and apparatus for analyzing a circuit model by reducing, and a computer program product for analyzing the circuit model. The circuit model at least includes independent current source models, resistance models, and capacitance models. Also, the circuit model forms a resistance capacitance (RC) network with independent current sources. The method includes selecting a node to be removed using resistance information and comparing conductance of a capacitor for a given time step and the total conductance of the node. Further, the method includes removing the selected nodes and generating RC elements and independent current sources using adjacent nodes, which maintain the accuracy of node voltages of a circuit reduced in an accuracy order used for entrywise perturbation of the corresponding circuit equation. Moreover, an efficient method of handling the independent current sources while reducing the circuit is provided.

Claims

1. A method of analyzing a circuit model by reduction, the method comprising:

inputting information about the circuit model, the information comprising a circuit net list with independent current sources and a node state information of each of a plurality of nodes in the circuit model;

selecting one of the nodes to be removed;

removing the selected node and generating a reduced circuit; and

post-processing a reduced circuit net list from intermediate data of the reduced circuit.

2. The method of claim 1, further comprising preprocessing the circuit net list with the independent current sources.

3. The method of claim 2, wherein the preprocessing comprises inputting an RC net list with independent current sources and node state information.

4. The method of claim 2, wherein the preprocessing comprises calculating an effective conductance of a capacitor for a given time step.

5. The method of claim 2, wherein the preprocessing comprises calculating a conductance of a node in the circuit.

6. The method of claim 2, wherein the preprocessing comprises selecting nodes to be removed for controlling an error and increasing reduction ratio.

7. The method of claim 6, wherein the selecting of nodes comprises sorting the nodes in order of degree of the nodes.

8. The method of claim 6, wherein the selecting of nodes comprises determining whether a node is to be removed by comparing the conductance of the capacitor and the sum of conductance of the nodes.

9. The method of claim 1, wherein the removing of the selected node comprises creating a resistor between each two nodes adjacent to the removed node.

10. The method of claim 1, wherein the removing of the selected node comprises creating grounded capacitor at each node adjacent to the removed node.

11. The method of claim 1, wherein the removing of the selected node comprises creating one of the independent current sources at each node adjacent to the removed node.

12. The method of claim 11, wherein the creating of the independent current sources comprises processing a symbolic name and a current scaling factor value of a piecewise linear (PWL) current source while reducing the circuit.

13. The method of claim 1, wherein the post-processing comprises generating the PWL current source using the symbolic name and the current scaling factor value after reducing the circuit.

14. A computer-readable medium having recorded thereon instructions executed by processing, the instructions for:

inputting information about an original circuit structure, the information comprising a circuit net list with independent current sources and node state information of each of a plurality of nodes in the circuit;

selecting one of the nodes to be removed;

removing the selected node and generating a reduced circuit; and

post-processing a reduced circuit net list from intermediate data of the reduced circuit.

15. A computer program product for performing a circuit simulation by realizing a reduced circuit of a power distribution network for simulating the power distribution network, the computer program product embodied on a computer-readable medium and comprising instructions, the instructions comprising:

inputting information about the circuit model, the information comprising a circuit net list with independent current sources and node state information of each of a plurality of nodes in the circuit;

selecting one of the nodes to be removed;

removing the selected node and generating a reduced circuit; and

post-processing a reduced circuit net list from intermediate data of the reduced circuit.

16. An apparatus for analyzing a circuit model by reduction, the apparatus comprising:

a processor;

a memory; and

instructions stored in the memory and executed by the processor, for;

inputting information about the circuit model, the information comprising a circuit net list with independent current sources and node state information of each of a plurality of nodes in the circuit;

selecting one of the nodes to be removed;

removing the selected node and generating a reduced circuit; and

post-processing a reduced circuit net list from intermediate data of the reduced circuit.