SYSTEM AND METHOD FOR SIGN-OFF TIMING CLOSURE OF A VLSI CHIP

• US 20080209376A1
• Filed: 02/28/2007
• Published: 08/28/2008
• Est. Priority Date: 02/28/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Villarrubia, Paul G., Trevillyan, Louise H., Kotecha, Pooja M., Matheny, Adam P., Kazda, Michael A., Reddy, Lakshmi
• Granted Patent: US 7,581,201 B2
• Time in Patent Office: Days
• US Class Current: 716/6
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, and asserted parasitic information. The method corrects violations in a placed and routed design of a VLSI circuit chip, where the design is represented by a netlist describing logical and physical characteristics of the design and by a corresponding timing graph, the method including the steps of: identifying violations in the design; iteratively eliminating the violations by incrementally transforming the logical and the physical characteristics of the design, incorporating in the design only legal placements and routes; and applying incremental timing to evaluate the transformations, and updating the existing timing graphs to reflect changes consisting of the legal placements and routes.

Claims

1. A method for correcting violations in a placed and routed design of a Very Large Scale Integrated (VLSI) circuit chip, said design being represented by a netlist describing logical and physical characteristics of said design and by a corresponding timing graph, the method comprising the steps of:

identifying violations in said design;

iteratively eliminating said violations by incrementally transforming the logical and the physical characteristics of the design, incorporating in said design only legal placements and routes; and

applying incremental timing to evaluate the transformations, and updating the existing timing graphs to reflect changes consisting of the legal placements and routes.

2. The method as recited in claim 1, wherein said violations are identified using timing graphs.

3. The method as recited in claim 2, wherein said violations are corrected in-situ.

4. The method as recited in claim 1, wherein said violations comprise transition time, capacitance, and timing violations.

5. The method of claim 1, further comprising the step of synchronizing path-based processes with incremental block-based timing to remove common path pessimism.

6. The method as recited in claim 1, wherein local transformations supply a displacement number that returns potential locations to place candidate standard cells into unoccupied space.

7. The method as recited in claim 6, wherein a physical location within an allowable displacement assigns the legal placement in which the candidate standard cell fits without overlapping.

8. The method as recited in claim 6, wherein routing of the standard cells comprises the step of localizing and minimizing wiring congestion.

9. The method as recited in claim 1, further comprising the step of modeling interconnects by incremental extraction.

10. The method as recited in claim 1, further comprising the step of performing an incremental coupling analysis to account for noise considerations affecting timing.

11. The method as recited in claim 1, wherein said routing further comprises the step of:

transacting log changes to restore said design to its original state when changes are discarded.

12. The method as recited in claim 1, wherein said changes are validated and accepted following the incremental placement, routing and extraction.

13. The method as recited in claim 1, wherein transforming said logical characteristics to eliminate said violations is achieved by measuring coupling effects and is followed by making changes resulting from performing an integrated coupling analysis.

14. The method as recited in claim 13, wherein said transforming of said logical characteristics takes place upon performing incremental statistical timing.

15. The method as recited in claim 14, wherein said transforming of said logical characteristics preserves SPICE parasitic data.

16. The method as recited in claim 1, wherein local transformations supply a displacement number that returns potential locations to fit candidate standard cells into occupied space, and further comprises displacing cells currently occupying the potential location to another legal location.

17. The method as recited in claim 16, wherein a physical location within an allowable displacement assigns the legal location wherein the standard cell fits without overlapping.

18. The method as recited in claim 1 further provides an abstract routing representation, including global routing to increase throughput during an early phase of design closure.

19. The method as recited in claim 1 further comprises the step of converting global routing information into detailed routing information when processing local transformations.

20. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for correcting violations in a placed and routed design of a Very Large Scale Integrated (VLSI) circuit chip, said design being represented by i) a netlist describing logical and physical characteristics of said design and ii) by a corresponding timing graph, the method comprising the steps of:

identifying violations in said design;

iteratively eliminating said violations by incrementally transforming the logical and the physical characteristics of the design, incorporating in said design only legal placements and routes; and

applying incremental timing to evaluate the transformations, and updating the existing timing graphs to reflect changes consisting of the legal placements and routes.