Array substrate for liquid crystal display device and method of fabricating the same
First Claim
1. An array substrate for a liquid crystal display device, comprising:
- a gate line on a substrate;
a gate insulating layer on the gate line;
a data line crossing the gate line;
a gate electrode connected to the gate line;
an active layer on the gate insulating layer and overlapping the gate electrode;
first and second ohmic contact layers on the active layer, the first and second ohmic contact layers spaced apart from each other by a first distance;
first and second barrier patterns spaced apart from each other by the first distance and on the first and second ohmic contact layers, respectively, wherein the active layer is exposed through the first and second barrier patterns;
source and drain electrodes spaced apart from each other by a second distance greater than the first distance and on the first and second barrier patterns, respectively, the source electrode being connected to the data line; and
a pixel electrode connected to the drain electrode.
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Accused Products
Abstract
An array substrate for a liquid crystal display device includes a gate line on a substrate; a gate insulating layer on the gate line; a data line crossing the gate line; a gate electrode connected to the gate line; an active layer on the gate insulating layer and overlapping the gate electrode; first and second ohmic contact layers on the active layer, the first and second ohmic contact layers spaced apart from each other by a first distance; first and second barrier patterns spaced apart from each other by the first distance and on the first and second ohmic contact layers, respectively. The active layer is exposed through the first and second barrier patterns; source and drain electrodes spaced apart from each other by a second distance greater than the first distance and on the first and second barrier patterns, respectively.
9 Citations
13 Claims
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1. An array substrate for a liquid crystal display device, comprising:
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a gate line on a substrate; a gate insulating layer on the gate line; a data line crossing the gate line; a gate electrode connected to the gate line; an active layer on the gate insulating layer and overlapping the gate electrode; first and second ohmic contact layers on the active layer, the first and second ohmic contact layers spaced apart from each other by a first distance; first and second barrier patterns spaced apart from each other by the first distance and on the first and second ohmic contact layers, respectively, wherein the active layer is exposed through the first and second barrier patterns; source and drain electrodes spaced apart from each other by a second distance greater than the first distance and on the first and second barrier patterns, respectively, the source electrode being connected to the data line; and a pixel electrode connected to the drain electrode. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of fabricating an array substrate for a liquid crystal display device, comprising:
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forming a gate line and a gate electrode on a substrate, the gate electrode connected to the gate line; forming a gate insulating layer on the gate electrode and the gate line; forming an active layer on the gate insulating layer, an impurity-doped amorphous silicon pattern on the active layer and a metal pattern on the impurity-doped amorphous silicon pattern on the active layer, each of the active layer, the impurity-doped amorphous silicon pattern and the metal pattern overlapping the gate electrode; forming a source electrode, a drain electrode and a data line, the source and drain electrodes on the metal pattern and spaced apart from each other by a first distance, the data line crossing the gate line and connected to the source electrode; etching the metal pattern and the impurity-doped amorphous silicon pattern to form first and second barrier patterns from the metal pattern under the source and drain electrodes and first and second ohmic contact layers under the first and second barrier patterns, wherein the first barrier pattern and the first ohmic contact pattern are spaced apart from the second barrier pattern and the second ohmic contact pattern by a second distance smaller than the first distance; and forming a pixel electrode connected to the drain electrode. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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Specification