CMOS IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME
First Claim
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1. An apparatus comprising:
- a first shallow trench isolation layer and a second shallow trench isolation layer formed in an epitaxial layer on both sides of a predetermined region of the epitaxial layer;
a poly gate contacting the first shallow trench isolation layer and the second shallow trench isolation layer and formed over the predetermined region of the epitaxial layer; and
a plurality of channels formed in the epitaxial layer and under the poly gate.
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Abstract
A CMOS image sensor that can include a first shallow trench isolation layer and a second shallow trench isolation layer formed in an epitaxial layer on both sides of a predetermined region of the epitaxial layer; a poly gate contacting the first shallow trench isolation layer and the second shallow trench isolation layer and formed over the predetermined region of the epitaxial layer; and a plurality of channels formed in the epitaxial layer and under the poly gate.
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Citations
20 Claims
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1. An apparatus comprising:
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a first shallow trench isolation layer and a second shallow trench isolation layer formed in an epitaxial layer on both sides of a predetermined region of the epitaxial layer; a poly gate contacting the first shallow trench isolation layer and the second shallow trench isolation layer and formed over the predetermined region of the epitaxial layer; and a plurality of channels formed in the epitaxial layer and under the poly gate. - View Dependent Claims (8, 9, 10)
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- 3. The apparatus of claim 3, wherein the poly gate is connected to the gate of the transfer transistor.
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11. A method comprising:
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forming a first channel and a second channel in a predetermined region of an epitaxial layer; forming a first shallow trench isolation layer and a second shallow trench isolation layer in an epitaxial layer on both sides of the predetermined region of the epitaxial layer; forming a first trench adjacent a first side of the predetermined region in the first shallow trench isolation layer and a second trench adjacent a second side of the predetermined region in the second shallow trench isolation layer; forming a pair of oxide films in the first and second trenches of the shallow trench isolation layers; forming a conductive film over each oxide film; forming a third channel in the predetermined region and extending substantially perpendicular relative to the first and second channels while also interconnecting the first and second channels; forming a gate oxide film over the predetermined region interconnecting the oxide films; and
thenforming a poly gate over the predetermined region of the epitaxial layer and each conductive film. - View Dependent Claims (12, 13, 14)
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15. A method comprising:
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forming a first plurality of trenches in an epitaxial layer; forming a first channel and a second channel in a predetermined region of the epitaxial layer; forming an oxide film in each one of the first plurality of trenches; forming a conductive film over the oxide film; forming a pair of device isolating layers by gap filling a silicon oxide film in each one of the second plurality of trenches using a CMP process; forming a third channel in the predetermined region and extending substantially perpendicular relative to the first and second channels while also interconnecting the first and second channels; forming a gate oxide film over the predetermined region interconnecting the oxide films; and
thenforming a poly gate over the conductive film and the gate oxide film. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification