CMOS IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME

• US 20080210992A1
• Filed: 12/26/2007
• Published: 09/04/2008
• Est. Priority Date: 12/29/2006
• Status: Abandoned Application

• Current Assignee: Dongbu HiTek Co., Ltd.
• Original Assignee: Dongbu HiTek Co., Ltd.
• Inventors: Kim, Tae-Gyu
• Application Number:
  US11/964,456
• Publication Number:
  US 20080210992A1
• Time in Patent Office: Days
• US Class Current: 257/292
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70

Abstract

A CMOS image sensor that can include a first shallow trench isolation layer and a second shallow trench isolation layer formed in an epitaxial layer on both sides of a predetermined region of the epitaxial layer; a poly gate contacting the first shallow trench isolation layer and the second shallow trench isolation layer and formed over the predetermined region of the epitaxial layer; and a plurality of channels formed in the epitaxial layer and under the poly gate.

Claims

1. An apparatus comprising:

a first shallow trench isolation layer and a second shallow trench isolation layer formed in an epitaxial layer on both sides of a predetermined region of the epitaxial layer;

a poly gate contacting the first shallow trench isolation layer and the second shallow trench isolation layer and formed over the predetermined region of the epitaxial layer; and

a plurality of channels formed in the epitaxial layer and under the poly gate.

8. The apparatus of claim 1, wherein the plurality of channels comprises a first channel and a second channel formed in opposing sides of the predetermined region of the epitaxial layer, and a third channel extending substantially perpendicular relative to the first and second channels and interconnecting the first and second channels.

9. The apparatus of claim 1, further comprising a gate oxide film provided between the poly gate and the region of the epitaxial layer.

10. The apparatus of claim 1, wherein the poly gate comprises at least one of poly silicon and an electrical conductive material.

3. The apparatus of claim 3, wherein the poly gate is connected to the gate of the transfer transistor.

2. The apparatus of claim 3, wherein a gate of a transfer transistor formed over the predetermined region of the epitaxial layer;

4. The apparatus of claim 3, wherein the poly gate comprises a first poly gate portion contacting the first shallow trench isolation layer, a second poly gate portion contacting the second shallow trench isolation layer, and a third poly gate portion extending substantially perpendicular relative to the first and second poly gate portions and also interconnecting the first and second poly gate portions.

5. The apparatus of claim 4, wherein the third poly gate portion is provided over the predetermined region of the epitaxial layer.

6. The apparatus of claim 5, wherein the plurality of channels comprises a first channel and a second channel formed in opposing sides of the predetermined region of the epitaxial layer, and a third channel extending substantially perpendicular relative to the first and second channels and interconnecting the first and second channels.

7. The apparatus of claim 6, wherein the first channel and the second channel formed extend substantially parallel to the first and second poly gate portions and the third channel extends substantially parallel to the third poly gate portion.

11. A method comprising:

forming a first channel and a second channel in a predetermined region of an epitaxial layer;

forming a first shallow trench isolation layer and a second shallow trench isolation layer in an epitaxial layer on both sides of the predetermined region of the epitaxial layer;

forming a first trench adjacent a first side of the predetermined region in the first shallow trench isolation layer and a second trench adjacent a second side of the predetermined region in the second shallow trench isolation layer;

forming a pair of oxide films in the first and second trenches of the shallow trench isolation layers;

forming a conductive film over each oxide film;

forming a third channel in the predetermined region and extending substantially perpendicular relative to the first and second channels while also interconnecting the first and second channels;

forming a gate oxide film over the predetermined region interconnecting the oxide films; and

then

forming a poly gate over the predetermined region of the epitaxial layer and each conductive film.

12. The method of claim 11, wherein forming the forming a first shallow trench isolation layer and the second shallow trench isolation layer comprises:

forming a first trench and a second trench in the epitaxial layer using an STI process before forming the first and second channels; and

then

gap filling a silicon oxide film in the first and second trenches after forming the first and second channels.

13. The method of claim 11, wherein forming the gate oxide film comprises:

forming a photoresist pattern over the epitaxial layer; and

then

depositing a silicon oxide film using the photoresist as a mask.

14. The method of claim 13, wherein the gate oxide film is formed over the predetermined region where a gate of a transfer transistor is formed. The second photoresist pattern can then be removed by an ashing process.

15. A method comprising:

forming a first plurality of trenches in an epitaxial layer;

forming a first channel and a second channel in a predetermined region of the epitaxial layer;

forming an oxide film in each one of the first plurality of trenches;

forming a conductive film over the oxide film;

forming a pair of device isolating layers by gap filling a silicon oxide film in each one of the second plurality of trenches using a CMP process;

forming a third channel in the predetermined region and extending substantially perpendicular relative to the first and second channels while also interconnecting the first and second channels;

forming a gate oxide film over the predetermined region interconnecting the oxide films; and

then

forming a poly gate over the conductive film and the gate oxide film.

16. The method of claim 15, wherein the predetermined region of the epitaxial layer is between the first plurality of trenches.

17. The method of claim 15, wherein forming the forming the conductive film comprises:

gap filling at least one of a polysilicon material and an electrical conductive material over the oxide film; and

then

planarizing the surface of the epitaxial layer.

18. The method of claim 15, wherein forming the pair of device isolating layers comprises:

forming a first photoresist pattern over the predetermined region;

forming a second plurality of trenches by removing a portion of the conductive film and the oxide film by an etching process using the first photoresist pattern;

gap filling a silicon oxide film in the second plurality of trenches; and

then

removing the first photoresist pattern.

19. The method of claim 18, wherein forming the gate oxide film comprises:

exposing the uppermost surface of the oxide films by forming a second photoresist pattern over the epitaxial layer;

depositing a silicon oxide film using the second photoresist pattern; and

then

removing the second photoresist pattern.

20. The method of claim 19, wherein forming the poly gate comprises:

exposing the conductive film and the gate oxide film by forming a third photo resist pattern;

depositing a polysilicon material over the conductive film and the gate oxide film and patterning the polysilicon material using the third photoresist pattern; and

then

removing the third photoresist pattern.