ULTRA DENSE TRENCH-GATED POWER DEVICE WITH THE REDUCED DRAIN-SOURCE FEEDBACK CAPACITANCE AND MILLER CHARGE

• US 20080211014A1
• Filed: 10/31/2007
• Published: 09/04/2008
• Est. Priority Date: 03/09/2001
• Status: Abandoned Application

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Zeng, Jun
• Application Number:
  US11/930,686
• Publication Number:
  US 20080211014A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/749 with turn-on by field effect
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.

Claims

1. A semiconductor device having improved and reduced Miller capacitance in a repeated cellular structure, wherein the cells of the device comprise:

a substrate having one surface with a first layer highly doped with a first conductivity dopant and forming a drain,

a second layer over the first layer and lightly doped with a first conductivity dopant,

a third layer over the second layer and doped with a second conductivity dopant opposite in polarity to the first conductivity component, and forming a PN junction with the second layer,

a fourth layer on the opposite surface of the semiconductor substrate and highly doped with a first conductivity dopant;

a trench structure extending from the fourth layer into the substrate and dividing the fourth layer into a plurality of source regions,

said trench having spaced apart sidewalls and a floor with an insulating layer having substantially uniform thickness on the sidewalls and floor, upper and lower conductive layers separated by a dielectric layer, and

wherein the second layer comprises a layer of dopant that curves upwardly toward the surface of the substrate proximate the sidewalls of the trench and the bottom of the upper layer of the trench conductor is at about the same level as the PN junction proximate the sidewall of the trench.

2. The semiconductor device of claim 1 further comprising a source metal layer over the device and in electrical contact with the fourth layer to contact the source regions and in electrical contact with the lower conductive layer of the trenches at peripheral locations around the cells of the device.

3. The semiconductor device of claim 2 wherein the source metal is in contact with the third layer of the second conductivity type.

4. A method for forming a semiconductor device with reduced Miller capacitance comprising the steps of:

heavily doping a substrate with a first conductivity dopant to form a drain region;

growing an epitaxial layer on the substrate and lightly doping the epitaxial layer with a dopant of the first conductivity;

implanting the surface of the epitaxial layer with dopants of a second polarity opposite in polarity to the first conductivity dopant;

covering the substrate with a trench mask having openings corresponding to desired trench regions and removing material from the exposed regions to form trenches;

growing an oxide layer on the trench walls and floor and diffusing the second conductivity dopant to form well regions adjacent the trench sidewalls;

forming over said oxide layer on said trench walls and floor upper and lower conductive layers respectively and separating the layers with a first dielectric layer;

forming source regions on the surface of the epitaxial layer with dopant of the first conductivity; and

adding a second interlevel dielectric layer above said upper conductive layer.