METHOD OF MANUFACTURING A SEMICONDUCTOR POWER DEVICE

• US 20080211015A1
• Filed: 01/08/2008
• Published: 09/04/2008
• Est. Priority Date: 07/08/2005
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Arena, Giuseppe, Magri, Angelo, Camalleri, Cateno Marco, Donato, Caterina
• Granted Patent: US 7,842,574 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench is formed in a semiconductor body, the side walls and the bottom of the trench covered with a first dielectric material layer, the trench filled with a second dielectric material layer, the first and the second dielectric material layers are etched via a partial, simultaneous, and controlled etching such that the dielectric materials have similar etching rates, a gate-oxide layer having a thickness smaller than the first dielectric material layer deposited on the walls of the trench, a gate region of conductive material formed within the trench, and body regions and source regions formed within the semiconductor body at the sides of and insulated from the gate region. Thereby, the gate region extends only on top of the remaining portions of the first and second dielectric material layers.

Claims

1. A process for manufacturing a semiconductor power device, comprising the steps of:

forming a semiconductor body of a first conductivity type and having a top surface;

forming, in said semiconductor body, a trench having side walls and a bottom;

coating said side walls and said bottom of said trench with a first dielectric material layer;

filling said trench with a second dielectric material layer;

etching said first dielectric material layer via an etching process;

forming a gate-oxide layer on said walls of said trench;

forming a gate region of conductive material within said trench and surrounded by said gate-oxide layer; and

forming, within said semiconductor body, a body region having a second conductivity type and a source region having said first conductivity type,

said first and second dielectric material layers comprising materials having similar responses to said etching process, and said etching step comprising simultaneously etching said first dielectric material layer and said second dielectric material layer so as to remove said first and second dielectric material layers in a partial, simultaneous and controlled way within said trench.

2. The process according to claim 1 wherein, at the end of said etching step, said trench houses, at the bottom, portions of said first dielectric material layer and of said second dielectric material layer, said portions having a depth that is approximately equal.

3. The process according to claim 1 wherein said etching step comprises removing said first and second dielectric material layers from said surface and continuing said etching step so as to remove a further portion of said first and second dielectric material layers.

4. The process according to claim 1 wherein said etching step comprises using a dry etching process.

5. The process according to claim 4 wherein said dry etching process comprises carrying out a plasma etch with a reactive gas.

6. The process according to claim 5 wherein said reactive gas comprises tetrafluoromethane (CF₄)/trifluoromethane (CHF₃)/argon.

7. The process according to claim 1 wherein said first dielectric material layer is TEOS (tetraethylorthosilicate) and said second dielectric material layer is silicon nitride.

8. The process according claim 1 wherein said step of forming a trench in said semiconductor body is followed by implanting dopant ion species and forming a modified-conductivity region underneath said trench.

9. The process according to claim 1 wherein said step of forming a gate region is followed by forming a metal layer on top of said gate region.

10. The process according to claim 9 wherein the step of forming a metal layer comprises a silicidation step using a metal from the group of cobalt, titanium, and tungsten.

11. The process according to claim 1 wherein said step of forming a source region comprises a blanket implantation of a dopant species.

12. The process according to claim 11 wherein said steps of forming a body region and a source region are followed by the steps of:

depositing an insulating layer on said surface;

forming an opening extending through said insulating layer and said source region and partially into said body region; and

filling said opening with metal.

13. The process according to claim 1 wherein said step of forming a gate region is followed by partially removing said conductive material within said trench and filling said trench with dielectric material.

14. The process according to claim 13 wherein said step of partially removing said conducting material is followed by a step of depositing a gate metallization layer.

15. The process according to claim 1, comprising, prior to said step of coating, forming an oxide layer.

16. The process according to claim 1 wherein said first dielectric material layer has a first thickness and said gate-oxide layer has a second thickness smaller than said first thickness.

17. A semiconductor power device, comprising:

a semiconductor body having a first conductivity type and a surface;

a trench, formed in said semiconductor body and having side walls;

an insulating region extending along a bottom portion of said side walls of said trench, said insulating region formed by a first dielectric material and having a first thickness;

a gate-oxide layer extending on said side walls of said trench and on top of said insulating region, said gate-oxide layer having a second thickness smaller than said first thickness;

a gate region of conductive material, extending within said trench and surrounded by said gate-oxide layer;

a body region of a second conductivity type, extending within said semiconductor body, at the sides of said gate-oxide layer and into said gate region;

a source region of said first conductivity type, extending within said semiconductor body at the sides of said gate-oxide layer and into said gate region and on top of said body region; and

a filling region of a second dielectric material, different from said first dielectric material, said filling region surrounded at the sides and at the bottom by said insulating region, said gate region extending on top of said filling region and said insulating region.

18. The device according to claim 17 wherein said filling region has a forked top profile.

19. The device according to claim 17 wherein said second dielectric material is silicon nitride.

20. The device according to claim 17, comprising a modified-conductivity region underneath said trench.

21. The device according to claim 17 wherein a metal region extends on said gate region.

22. The semiconductor power device according to claim 17, comprising a dielectric material layer extending on top of said surface;

an opening extending through said dielectric layer and said source region; and

a source metallization layer extending on top of said dielectric layer and within said opening and said source region, as far as said body region, said source metallization layer electrically connecting said source region and said body region.

23. The device according to claim 17 wherein said gate region has a top surface extending at a lower level with respect to said surface of said body and is overlaid by a region of dielectric material.

24. The device according to claim 17 wherein a source metallization layer is on top of said surface and is in electrical contact with said source region.

25. A semiconductor power device comprising:

a semiconductor body;

a trench, having a bottom and sidewalls, located in the semiconductor body;

a first dielectric layer positioned along the bottom and a lower portion of the sidewalls of the trench;

a first dielectric region positioned on top of the first dielectric layer and having a gap located therein;

a second dielectric region in the gap;

a second dielectric layer positioned on the sidewalls of the trench;

a gate region of conductive material located within the trench above the first and second dielectric regions and having a top surface;

a source region of a first conductivity type positioned in the semiconductor body and adjacent to the second dielectric layer and having a top surface; and

a body region of a second conductivity type positioned in the semiconductor body and adjacent to the second dielectric layer;

26. The device according to claim 25 wherein the second dielectric region has a forked top profile.

27. The device according to claim 25 comprising a modified conductivity region underneath the trench;

28. The device according to claim 25 wherein a metal region extends on top of the gate region.

29. The device according to claim 25 comprising:

a third dielectric layer formed above the gate, body, and source regions and having a gap extending through the source region to the body region;

a source metallization layer positioned on top of the third dielectric layer and extending through the third dielectric layer and the source region to electrically connect the body and source regions to one another;

30. The device according to claim 25 wherein the top surface of the gate region is lower than the top surface of the source region and is overlaid by a dielectric material.

31. The device according to claim 25 wherein a source metallization layer is positioned on top of the semiconductor body and is in electrical contact with the source region.

32. The device according to claim 25 wherein the bottom of the trench is rounded and the trench has a U-shaped profile.

33. A method, comprising:

forming a trench in a semiconductor body;

coating side walls and a bottom of the trench with a first dielectric material;

forming an oxide layer on the first dielectric material layer;

filling the trench with a second dielectric material; and

removing a portion of the first dielectric material layer, the oxide, and the second dielectric material using an etching process that simultaneously and partially removes the first dielectric material layer, the oxide, and the second dielectric material.

34. The method of claim 33, comprising the further steps of:

forming a gate oxide layer on the walls of the trench exposed by the etching process;

filling the trench with a conductive material to form a gate region; and

forming in the semiconductor body a body region and a source region.

35. The method of claim 33 wherein the first dielectric material comprises TEOS (tetraethylorthosilicate) and the second dielectric material comprises silicon nitride.

36. The method of claim 34 wherein the step of forming a trench in the semiconductor body is followed by implanting dopant ion species to form a modified conductivity region underneath the trench.