METHOD OF MANUFACTURING A SEMICONDUCTOR POWER DEVICE
First Claim
1. A process for manufacturing a semiconductor power device, comprising the steps of:
- forming a semiconductor body of a first conductivity type and having a top surface;
forming, in said semiconductor body, a trench having side walls and a bottom;
coating said side walls and said bottom of said trench with a first dielectric material layer;
filling said trench with a second dielectric material layer;
etching said first dielectric material layer via an etching process;
forming a gate-oxide layer on said walls of said trench;
forming a gate region of conductive material within said trench and surrounded by said gate-oxide layer; and
forming, within said semiconductor body, a body region having a second conductivity type and a source region having said first conductivity type,said first and second dielectric material layers comprising materials having similar responses to said etching process, and said etching step comprising simultaneously etching said first dielectric material layer and said second dielectric material layer so as to remove said first and second dielectric material layers in a partial, simultaneous and controlled way within said trench.
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Accused Products
Abstract
A trench is formed in a semiconductor body, the side walls and the bottom of the trench covered with a first dielectric material layer, the trench filled with a second dielectric material layer, the first and the second dielectric material layers are etched via a partial, simultaneous, and controlled etching such that the dielectric materials have similar etching rates, a gate-oxide layer having a thickness smaller than the first dielectric material layer deposited on the walls of the trench, a gate region of conductive material formed within the trench, and body regions and source regions formed within the semiconductor body at the sides of and insulated from the gate region. Thereby, the gate region extends only on top of the remaining portions of the first and second dielectric material layers.
10 Citations
36 Claims
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1. A process for manufacturing a semiconductor power device, comprising the steps of:
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forming a semiconductor body of a first conductivity type and having a top surface; forming, in said semiconductor body, a trench having side walls and a bottom; coating said side walls and said bottom of said trench with a first dielectric material layer; filling said trench with a second dielectric material layer; etching said first dielectric material layer via an etching process; forming a gate-oxide layer on said walls of said trench; forming a gate region of conductive material within said trench and surrounded by said gate-oxide layer; and forming, within said semiconductor body, a body region having a second conductivity type and a source region having said first conductivity type, said first and second dielectric material layers comprising materials having similar responses to said etching process, and said etching step comprising simultaneously etching said first dielectric material layer and said second dielectric material layer so as to remove said first and second dielectric material layers in a partial, simultaneous and controlled way within said trench. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A semiconductor power device, comprising:
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a semiconductor body having a first conductivity type and a surface; a trench, formed in said semiconductor body and having side walls; an insulating region extending along a bottom portion of said side walls of said trench, said insulating region formed by a first dielectric material and having a first thickness; a gate-oxide layer extending on said side walls of said trench and on top of said insulating region, said gate-oxide layer having a second thickness smaller than said first thickness; a gate region of conductive material, extending within said trench and surrounded by said gate-oxide layer; a body region of a second conductivity type, extending within said semiconductor body, at the sides of said gate-oxide layer and into said gate region; a source region of said first conductivity type, extending within said semiconductor body at the sides of said gate-oxide layer and into said gate region and on top of said body region; and a filling region of a second dielectric material, different from said first dielectric material, said filling region surrounded at the sides and at the bottom by said insulating region, said gate region extending on top of said filling region and said insulating region. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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25. A semiconductor power device comprising:
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a semiconductor body; a trench, having a bottom and sidewalls, located in the semiconductor body; a first dielectric layer positioned along the bottom and a lower portion of the sidewalls of the trench; a first dielectric region positioned on top of the first dielectric layer and having a gap located therein; a second dielectric region in the gap; a second dielectric layer positioned on the sidewalls of the trench; a gate region of conductive material located within the trench above the first and second dielectric regions and having a top surface; a source region of a first conductivity type positioned in the semiconductor body and adjacent to the second dielectric layer and having a top surface; and a body region of a second conductivity type positioned in the semiconductor body and adjacent to the second dielectric layer; - View Dependent Claims (26, 27, 28, 29, 30, 31, 32)
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33. A method, comprising:
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forming a trench in a semiconductor body; coating side walls and a bottom of the trench with a first dielectric material; forming an oxide layer on the first dielectric material layer; filling the trench with a second dielectric material; and removing a portion of the first dielectric material layer, the oxide, and the second dielectric material using an etching process that simultaneously and partially removes the first dielectric material layer, the oxide, and the second dielectric material. - View Dependent Claims (34, 35, 36)
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Specification