Pseudo-differential output driver with high immunity to noise and jitter
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Accused Products
Abstract
Circuits and methods are provided for transmitting a pseudo-differential output signal with relatively high immunity to noise and jitter. The output driver of the invention receives two differential input signals and outputs a single output signal with low voltage transistors and programmable impedance and on-die termination circuits. The pseudo-differential output driver consumes little circuit area and has low output capacitance.
57 Citations
21 Claims
- 1. (canceled)
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2. A circuit for transmitting an output signal, said circuit comprising:
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a first impedance operative to receive a first voltage, wherein said first impedance comprises first resistor circuitry whose resistance is adjustable responsive to a voltage of a first resistance control signal; switching circuitry coupled to said first impedance, said switching circuitry comprising a first path and a second parallel path, said switching circuitry operative to receive first and second differential input signals at said first and second paths, respectively, and to generate said output signal at a node in only one of said paths, without generating another output signal in another of said paths, in response to receipt of said first and second differential input signals; and a second impedance coupled to said switching circuitry and operative to receive a second voltage, wherein said second impedance comprises second resistor circuitry whose resistance is adjustable responsive to a voltage of a second resistance control signal. - View Dependent Claims (3, 4, 5)
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11. A method for transmitting an output signal from a driver circuit, said method comprising:
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receiving a first differential input signal at a first path; receiving a second differential input signal at a second parallel path, said second differential input signal complementary to said first differential input signal; driving said output signal at a node in only one of said paths, without driving another output signal in another of said paths, a voltage of said driven output signal being indicative of a difference in voltages of said first and second differential input signals; and disabling first on-die termination circuitry coupled in series to said first and second parallel paths by applying a first enable/disable signal to said first on-die termination circuitry. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A system comprising:
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a processor; a memory controller; a dynamic random access memory device comprising an array of memory cells and a circuit for transmitting an output signal, said circuit comprising; a source of relatively low voltage; a first impedance operative to receive a first voltage, wherein said first impedance comprises first resistor circuitry whose resistance is adjustable responsive to a voltage of a first resistance control signal; switching circuitry coupled to said first impedance, said switching circuitry comprising a first path and a second parallel path, said switching circuitry operative to receive first and second differential input signals at said first and second paths, respectively, and to generate said output signal at a node in only one of said paths, without generating another output signal in another of said paths, in response to receipt of said first and second differential input signals; and a second impedance coupled to said switching circuitry and operative to receive a second voltage, wherein said second impedance comprises second resistor circuitry whose resistance is adjustable responsive to a voltage of a second resistance control signal. - View Dependent Claims (18, 19, 20)
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21. A circuit for transmitting an output signal from a driver circuit, said circuit comprising:
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means for receiving a first differential input signal at a first path; means for receiving a second differential input signal at a second parallel path, said second differential signal complementary to said first differential signal; means for driving said output signal at a node in only one of said paths, without driving another output signal in another of said paths, a voltage of said driven output signal being indicative of a difference in voltages of said first and second differential input signals; and means for disabling first on-die termination circuitry coupled in series to said first and second parallel paths by applying a first enable/disable signal to said first on-die termination circuitry.
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Specification