Precision voltage level shifter based on thin gate oxide transistors

• US 20080211541A1
• Filed: 08/16/2007
• Published: 09/04/2008
• Est. Priority Date: 03/02/2007
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chauhan, Rajat
• Application Number:
  US11/893,637
• Publication Number:
  US 20080211541A1
• Time in Patent Office: Days
• US Class Current: 326/68
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A precision voltage level shifter based on thin gate oxide transistors is disclosed. A method of a voltage level shifter includes serially connecting thin n-channel gate oxide semiconductor FETs to think n-channel gate oxide semiconductor FETs to enable the voltage level shifter with a low input voltage. The method further includes permanently turning on a thick p-channel gate oxide semiconductor FET through grounding a gate of the thick p-channel gate oxide semiconductor FET to enable the voltage level shifter with an input voltage close to the I/O voltage of the voltage level shifter.

Claims

1. A voltage level shifter, comprising:

a plurality of gate oxide semiconductor field effect transistors (FETs) to translate an input voltage to an output voltage,

wherein a number of thin gate oxide semiconductor FETs of the plurality of gate oxide semiconductor FETs to connect with a number of thick gate oxide semiconductor FETs of the plurality of gate oxide semiconductor FETs.

2. The voltage level shifter of claim 1, wherein the plurality of gate oxide semiconductor FETs to comprise at least one of a p-channel gate oxide semiconductor FET and a n-channel gate oxide semiconductor FET.

3. The voltage level shifter of claim 1, wherein the number of thin gate oxide semiconductor FETs to enable the voltage level shifter to perform with the input voltage approximately at 0.9 volt.

4. The voltage level shifter of claim 1, further comprising a feedback loop to connect the output voltage of the voltage level shifter to one of the plurality of gate oxide semiconductor FETs to minimize power dissipation in the voltage level shifter.

5. The voltage level shifter of claim 1, further comprising at least one pair of thick gate oxide semiconductor FETs connected to the voltage level shifter with their gates connected to a low voltage supply to increase a limit of the output voltage.

6. The voltage level shifter of claim 5, wherein the low voltage supply supplies 1 volt and the limit of the output voltage is 2.5 volts.

7. A circuit, comprising:

a first transistor group to have a thick p-channel gate oxide FET, a thick n-channel gate oxide FET, and a thin n-channel gate oxide FET in series, wherein a gate of the thin n-channel gate oxide FET is connected to an input voltage, and a gate of the thick p-channel oxide FET is connected to a ground voltage;

a second transistor group to have a thick p-channel gate oxide FET, a thick n-channel gate oxide FET, and a thin n-channel gate oxide FET in series, wherein a gate of the thin n-channel gate oxide FET is connected to an inverse of the input voltage, a drain of the thick p-channel gate oxide FET of the first transistor group is connected to a gate of the thick p-channel gate oxide FET of the second transistor group, and a gate of the thick n-channel gate oxide FET is connected to an I/O voltage; and

a third transistor group to have a thick p-channel gate oxide FET, wherein a drain of the thick p-channel gate oxide FET is connected to a drain of the thick p-channel gate oxide FET of the second transistor group, and a gate of the thick p-channel gate oxide FET is connected to a feedback signal of the circuit; and

a feedback loop to connect the feedback signal to a gate of the thick n-channel gate oxide FET of the first transistor group.

8. The circuit of claim 7, wherein the I/O voltage is 1.8 volt and the input voltage is no less than 0.9 volt.

9. The circuit of claim 7, wherein the gate of the thick p-channel gate oxide FET of the first transistor group is connected to the ground voltage to enable the circuit to have the input voltage close to the I/O voltage.

10. The circuit of claim 7, wherein the thin n-channel gate oxide FET of the first transistor group and the thin n-channel gate oxide FET of the second transistor group to allow the circuit to have the input voltage of 0.9 volt.

11. The circuit of claim 7, further comprising a first inverter to inversely convert the input voltage to feed to the gate of the thin n-channel gate oxide FET of the second transistor group.

12. The circuit of claim 11, further comprising a second inverter to inversely convert a voltage obtained at the drain of the thick p-channel gate oxide FET of the second transistor group.

13. The circuit of claim 12, further comprising a third inverter to inversely convert the feedback signal to generate the output voltage.

14. The circuit of claim 13, further comprising a pair of additional thick n-channel gate oxide FETs added to the circuit to increase the I/O voltage.

15. The circuit of claim 14, further comprising a low voltage supply to connect to gates of the pair of additional thick n-channel gate oxide FETs.

16. The circuit of claim 15, wherein the low supply voltage supplies 1 volt to the gates of the pair of additional thick n-channel gate oxide FETs.

17. The circuit of claim 16, wherein the pair of additional thick n-channel gate oxide FETs to increase the I/O voltage up to 2.5 volts without aging the thin n-channel gate oxide FETs.

18. The circuit of claim 7, further comprising replacing the thick p-channel gate oxide FET of the first transistor group with at least one resistor.

19. A method of a voltage level shifter, comprising:

serially connecting thin n-channel gate oxide semiconductor FETs to thick n-channel gate oxide semiconductor FETs to enable the voltage level shifter with a low input voltage; and

permanently turning on a thick p-channel gate oxide semiconductor FET through grounding a gate of the thick p-channel gate oxide semiconductor FET to enable the voltage level shifter with an input voltage close to an I/O voltage of the voltage level shifter.

20. The method of claim 19, further comprising connecting additional thick n-channel oxide semiconductor FETs in series with the thin n-channel gate oxide semiconductor FETs to increase an output voltage of the voltage level shifter.