Mute Circuit

• US 20080211565A1
• Filed: 04/08/2008
• Published: 09/04/2008
• Est. Priority Date: 09/29/2005
• Status: Active Grant

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Yamamoto, Makoto, Shimomura, Kazuhiro
• Granted Patent: US 7,579,893 B2
• Time in Patent Office: Days
• US Class Current: 327/389
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

AnNchMOS transistor (1) is provided for muting of an output terminal (10) to which positive and negative output signals are outputted, and a mute switch circuit (3) is provided for controlling on/off of the transistor (1) by switching a voltage applied to the gate of the transistor (1). When muting is turned off, the back gate of the transistor (1) is biased by resistance division between resistors (R1 and R2) connected in series between the output terminal (10) and a predetermined negative potential (VSS).

Claims

1. (canceled)

2. A mute circuit for muting positive and negative output signals outputted to an output terminal,

the mute circuit, comprising:

an NchMOS transistor having a drain connected to the output terminal and a source connected to a ground potential;

a mute switch circuit for controlling on/off of the NchMOS transistor by switching a gate voltage of the NchMOS transistor to a power supply potential or a negative potential;

a resistor having one end connected to the output terminal; and

a predetermined number of diodes connected in series in a forward direction,

wherein a junction point between an other end of the resistor and an anode side of the diodes is connected to a back gate of the NchMOS transistor, and a cathode side of the diodes is connected to the negative potential.

3-4. -4. (canceled)

5. A mute circuit for muting positive and negative output signals outputted to an output terminal, comprising:

a NchMOS transistor having a drain connected to the output terminal and a source connected to a ground potential;

a mute switch circuit for controlling on/off of the NchMOS transistor by switching a gate voltage of the NchMOS transistor changes in accordance with the output signals while the NchMOS transistor is off.

wherein a back gate voltage of the NchMOS transistor changes in accordance with the output signals while the NchMOS transistor is off.

6. The mute circuit according to claim 5, furthermore comprising:

a resistor having one end connected to the output terminal; and

a predetermined number of diodes connected in series in a forward direction,

wherein a junction point between an other end of the resistor and an anode side of the diodes is connected to a back gate of the NchMOS transistor, and a cathode side of the diodes is connected to the negative potential.