Liquid Crystal Display and Gate Driving Circuit Thereof

• US 20080211760A1
• Filed: 10/31/2007
• Published: 09/04/2008
• Est. Priority Date: 12/11/2006
• Status: Abandoned Application

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Lee, Min Cheol, Baek, Seung-Soo, Jeon, Sang Jin, Kim, Young Bum, Lee, Yong Soon
• Application Number:
  US11/932,532
• Publication Number:
  US 20080211760A1
• Time in Patent Office: Days
• US Class Current: 345/98
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET

Abstract

A liquid crystal display and a dual gate driving circuit therefor wherein the number of signal lines are reduced by sharing a start pulse and an output signal of a dummy stage. The liquid crystal display includes a timing controller generating an output enable signal, a gate clock, and a signal start signal in response to an external input signal, a level shifter generating a gate clock pulse and a gate clock bar pulse in response to the output enable signal and the gate clock and generating a single start pulse in response to the start signal and the gate clock, and first and second gate driving circuits outputting the gate clock pulse or the gate clock bar pulse as a gate driving signal to the plurality of gate lines in response to the single start pulse.

Claims

1. A gate driving circuit comprising:

a circuit unit having a plurality of stages dependently connected to each other to output a gate clock pulse or a gate clock bar pulse as a gate driving signal for each of the gate lines in response to a single start pulse; and

a line unit having a start pulse line receiving the start pulse to provide the received start pulse to an input terminal of each of a first odd-numbered stage and a first even-numbered stage of the stages,

wherein output terminals of the stages are connected to the gate lines, respectively.

2. The gate driving circuit of claim 1, wherein odd-numbered stages of the stages output the gate clock pulse as the gate driving signal and wherein even-numbered stages of the stages output the gate clock bar pulse as the gate driving signal.

3. The gate driving circuit of claim 2, wherein each input terminal of the stages is connected to a carry terminal of a previous stage and wherein each control terminal of the stages is connected to an output terminal of a next stage.

4. The gate driving circuit of claim 3, wherein the odd-numbered stages include a first dummy stage having the carry terminal connected to the control terminal of the last odd-numbered stage and wherein the even-numbered stages include a second dummy stage having the carry terminal connected to the control terminal of the last even-numbered stage.

5. The gate driving circuit of claim 4, wherein the line unit comprises:

a first reset line connecting an output terminal of the first dummy stage to a reset terminal of each of the odd-numbered stages; and

a second reset line connecting an output terminal of the second dummy stage to a reset terminal of each of the even-numbered stages.

6. The gate driving circuit of claim 4, wherein the line unit includes a reset line connecting an output terminal of the second dummy stage to reset terminals of the stages and wherein the second dummy stage provides a reset signal to the reset line via the output terminal.

7. The gate driving circuit of claim 6, wherein the second dummy stage includes a pull-up transistor for providing the reset signal and wherein the pull-up transistor has a size larger than that of a pull-up transistor of each of the other stages.

8. A liquid crystal display comprising:

a timing controller generating an output enable signal, a gate clock, and a single start signal in response to an external input signal;

a level shifter generating a gate clock pulse and a gate clock bar pulse in response to the output enable signal and the gate clock and generating a single start pulse in response to the start signal and the gate clock; and

first and second gate driving circuits outputting the gate clock pulse or the gate clock bar pulse as a gate driving signal to be provided to a plurality of gate lines in response to the single start pulse.

9. The liquid crystal display of claim 8, wherein the first and second gate driving circuits are integrated on a liquid crystal display panel having the gate lines formed thereon and are formed at both ends of the gate lines to dually drive the gate lines.

10. The liquid crystal display of claim 9, wherein each of the first and second gate driving circuits includes a plurality of stages dependently connected to each other and wherein output terminals of the stages are connected to the gate lines, respectively.

11. The liquid crystal display of claim 10, wherein each of odd-numbered stages of the stages outputs the gate clock pulse as the gate driving signal and wherein each of even-numbered stages of the stages outputs the gate clock bar pulse as the gate driving signal.

12. The liquid crystal display of claim 11, wherein an input terminal of each of the stages is connected to a carry terminal of a previous stage and wherein a control terminal of each of the stages is connected to an output terminal of a next stage.

13. The liquid crystal display of claim 12, wherein the odd-numbered stages include a first dummy stage having a carry terminal connected to a control terminal of the last odd-numbered stage and wherein the even-numbered stages include a second dummy stage having a carry terminal connected to a control terminal of the last even-numbered stage.

14. The liquid crystal display of claim 13, wherein a reset terminal of each of the odd-numbered stages is connected to an output terminal of the first dummy stage and wherein a reset terminal of each of the even-numbered stages is connected to an output terminal of the second dummy stage.

15. The liquid crystal display of claim 13, wherein a reset terminal of each of the stages is connected to an output terminal of the second dummy stage.

16. The liquid crystal display of claim 15, wherein the second dummy stage includes a pull-up transistor connected to the reset terminal and wherein the pull-up transistor has a size larger than that of a pull-up transistor of each of the other stages.

17. The liquid crystal display of claim 9, further comprising a power supply for supplying a gate-on voltage and a gate-off voltage to the level shifter and wherein the level shifter outputs the gate clock pulse, the gate clock bar pulse and the start pulse as a gate-on voltage level and a gate-off voltage level.

18. The liquid crystal display of claim 17, wherein the level shifter comprises:

a first level shifting unit outputting the gate clock pulse by performing a logical operation on the output enable signal and the gate clock and amplifying a voltage level; and

a second level shifting unit outputting the gate clock bar pulse by performing a logical operation on the output enable signal and the gate clock, inverting a phase, and amplifying a voltage level.

19. The liquid crystal display of claim 18, wherein the first level shifting unit comprises:

a logical operation unit performing an OR operation on the output enable signal and the gate clock;

a driving inverter inverting the phase of the output of the logical operation unit and amplifying it; and

a full-swing inverter generating the gate clock pulse of the gate-on voltage level and the gate-off voltage level in response to an output of the driving inverter.

20. The liquid crystal display of claim 18, wherein the second level shifting unit comprises:

a logical operation unit for performing an OR operation on the output enable signal and the gate clock;

an inversion inverter inverting the phase of the output of the logical operation unit;

a driving inverter inverting the phase of the output of the inversion inverter and amplifying it; and

a full-swing inverter generating the gate clock bar pulse of the gate-on voltage level and the gate-off voltage level in response to an output of the driving inverter.