BIASED SENSING MODULE

• US 20080212354A1
• Filed: 09/18/2007
• Published: 09/04/2008
• Est. Priority Date: 09/18/2006
• Status: Active Grant

• Current Assignee: STMicroelectronics Pvt Ltd. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Pvt Ltd. (STMicroelectronics NV)
• Inventors: Ahmad, Nasim, Roy, Tanmoy
• Granted Patent: US 7,791,970 B2
• Time in Patent Office: Days
• US Class Current: 365/94
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A circuit includes a first pre-charge module, a first multiplexer module, a second pre-charge module, a second multiplexer module, a sense amplifier circuit, a third pre-charge module, an output module. The circuit is operatively coupled to a first core block and a second core block to provide the desired matching characteristics. The first core block and the second core block are memory blocks used for storing data bits for read-write operations. The circuit utilizes a unique operational coupling with one of the core blocks to provide the matching characteristics.

Claims

1-16. -16. (canceled)

17. A sensing circuit comprising:

a first pre-charge module and a first core block coupled thereto;

a first pass transistor;

a first multiplexer module coupled between said first pre-charge module and said first pass transistor;

a second pre-charge module and a second core block coupled thereto;

a second pass transistor;

a second multiplexer module coupled between said second pre-charge module and said second pass transistor;

a sense amplifier circuit coupled between said first multiplexer module and said second multiplexer module and having first and second inputs to receive inputs through said first pass transistor and said second pass transistor, respectively;

a third pre-charge module coupled to said first and second inputs of said sense amplifier circuit.

18. The sensing circuit of claim 17, further comprising an output module coupled to said sense amplifier and to provide an output signal.

19. The sensing circuit of claim 17, wherein said first pre-charge module comprises at least one PMOS transistor.

20. The sensing circuit of claim 17, wherein said second pre-charge module comprises at least one PMOS transistor.

21. The sensing circuit of claim 17, wherein said first pass transistor comprises a PMOS transistor.

22. The sensing circuit of claim 17, wherein said second pass transistor comprises a PMOS transistor.

23. The sensing circuit of claim 17, wherein said third pre-charge module comprises:

a third pass transistor having a source terminal coupled to a voltage source, a drain terminal coupled to said first input of said sense amplifier, and a gate terminal coupled to a node;

a fourth pass transistor having a source terminal coupled to said voltage source, a drain terminal coupled to the second input of the sense amplifier, and a gate terminal coupled to the gate terminal of the third pass transistor through the node; and

a fifth pass transistor having a source terminal coupled to the drain terminal of the fourth pass transistor, a drain terminal coupled to the drain terminal of the third transistor, and a gate terminal coupled to the gate of the third pass transistor and the fourth pass transistor through said node.

24. The sensing circuit of claim 23, wherein said third pass transistor comprises a PMOS transistor.

25. The sensing circuit of claim 23, wherein said fourth pass transistor comprises a PMOS transistor.

26. The circuit of claim 23, wherein said fifth pass transistor comprises a PMOS transistor.

27. A sense amplifier circuit comprising:

a latch circuit comprising a first inverter circuit and a second inverter circuit cross-coupled thereto;

a first pull down transistor coupled to said latch circuit to receive a first control signal;

a first pass transistor coupled to said first inverter circuit;

a second pass transistor coupled to said second inverter circuit; and

a second pull down transistor coupled to said first pass transistor and said second pass transistor to receive a second control signal.

28. The sense amplifier circuit of claim 27, wherein said first pull down circuit comprises an NMOS transistor.

29. The sense amplifier circuit of claim 27, wherein said second pull down circuit comprises an NMOS transistor.

30. The sense amplifier circuit of claim 27, wherein said first pass transistor comprises an NMOS transistor.

31. The sense amplifier circuit of claim 27, wherein said second pass transistor comprises an NMOS transistor.

32. A read only memory (ROM) comprising:

a plurality of memory blocks for storing data bits; and

a biased sensing circuit coupled to said plurality of memory blocks comprising

a first pre-charge module and a first core block coupled thereto,

a first pass transistor,

a first multiplexer module coupled between said first pre-charge module and said first pass transistor,

a second pre-charge module and a second core block coupled thereto,

a second pass transistor,

a second multiplexer module coupled between the second pre-charge module and said second pass transistor,

a sense amplifier circuit coupled between said first multiplexer module and said second multiplexer module and having first and second inputs to receive inputs through said first pass transistor and said second pass transistor, respectively, and

a third pre-charge module coupled to said first and second inputs of said sense amplifier circuit.

33. The ROM of claim 32, wherein said biased sensing circuit further comprises an output module coupled to said sense amplifier to provide an output signal.

34. The ROM of claim 32, wherein said first pre-charge module comprises at least one PMOS transistor;

and wherein said second precharge module comprises at least one PMOS transistor.

35. The ROM of claim 32, wherein said first pass transistor comprises a PMOS transistor;

and wherein said second pass transistor comprises a PMOS transistor.

36. The ROM of claim 32, wherein said third pre-charge module comprises:

a third pass transistor having a source terminal coupled to a voltage source, a drain terminal coupled to said first input of said sense amplifier, and a gate terminal coupled to a node;

a fourth pass transistor having a source terminal coupled to said voltage source, a drain terminal coupled to the second input of the sense amplifier, and a gate terminal coupled to the gate terminal of the third pass transistor through the node; and

a fifth pass transistor having a source terminal coupled to the drain terminal of the fourth pass transistor, a drain terminal coupled to the drain terminal of the third transistor, and a gate terminal coupled to the gate of the third pass transistor and the fourth pass transistor through said node.

37. A method of sensing through a sensing circuit comprising:

precharging input nodes, output nodes, and sensing branches of the sensing circuit;

selecting one of a first core block and a second core block through a selection line;

applying a clock signal to turn off pre-charge modules to conduct through a selected multiplexer module to allow an input signal to enter into one of the first core block and the second core block;

inverting the input signal when the input signal enters the second core block; and

multiplexing the outputs with a select signal when the input signal does not enter the second core block.

38. The method of claim 37, wherein at least one of the pre-charge modules comprises a PMOS transistor.

39. The method of claim 37, wherein the first core block comprises a NAND block.

40. The method of claim 37, wherein the second core block comprises a NAND block.

41. A method of making a circuit for sensing signals comprising:

coupling a first pre-charge module between a first core block and a first multiplexer;

coupling a second pre-charge module between a second core block and a second multiplexer;

coupling a first pass transistor coupled between the first multiplexer and a first input of a sense amplifier;

coupling a second pass transistor between the second multiplexer and a second input of the sense amplifier;

coupling a third pre-charge module to the first and second inputs of the sense amplifier; and

coupling an output module to the sense amplifier;

the sense amplifier to receive signals through the first and second pass transistors.

42. The method of claim 41, wherein the first pre-charge module comprises at least one PMOS transistor.

43. The method of claim 41, wherein the first pass transistor comprises a PMOS transistor.

44. The method of claim 41, wherein the third pre-charge module comprises:

a third pass transistor having a source terminal coupled to a voltage source, a drain terminal coupled to the first input of the sense amplifier, and a gate terminal coupled to a node;

a fourth pass transistor having a source terminal coupled to the voltage source, a drain terminal coupled to the second input of the sense amplifier, and a gate terminal coupled to the gate terminal of the third pass transistor through the node; and

a fifth pass transistor having a source terminal coupled to the drain terminal of the fourth pass transistor, a drain terminal coupled to the drain terminal of the third transistor, and a gate terminal coupled to the gate of the third pass transistor and the fourth pass transistor through the node.