NONVOLATILE NANOTUBE DIODES AND NONVOLATILE NANOTUBE BLOCKS AND SYSTEMS USING SAME AND METHODS OF MAKING SAME
First Claim
1. A memory array comprising:
- a plurality of word lines;
a plurality of bit lines;
a plurality of memory cells, each memory cell responsive to electrical stimulus on a word line and on a bit line, each memory cell including;
a two-terminal non-volatile nanotube switching device comprising a first and a second terminal, a semiconductor diode element, and a nanotube fabric article, the semiconductor diode and a nanotube article disposed between and in electrical communication with the first and second terminals,wherein the nanotube fabric article is capable of a plurality of resistance states, andwherein the first terminal is coupled to the word line and the second terminal is coupled to the bit line, the electrical stimulus applied to the first and second terminals capable of changing the resistance state of the nanotube fabric article; and
a memory operation circuit operably coupled to each bit line of the plurality of bit lines and each word line of the plurality of word lines,said operation circuit capable of selecting each of the cells by activating at least one of the bit line and the word line coupled to that cell to apply a selected electrical stimulus to each of the corresponding first and second terminals,said operation circuit further capable of detecting a resistance state of the nanotube fabric article of a selected memory cell and adjusting the electrical stimulus applied to each of the corresponding first and second terminals in response to the resistance state to controllably induce a selected resistance state in the nanotube fabric article;
wherein the selected resistance state of the nanotube fabric article of each memory cell corresponds to an informational state of said memory cell.
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Accused Products
Abstract
Under one aspect, a memory array includes word lines; bit lines; memory cells; and a memory operation circuit. Each memory cell responds to electrical stimulus on a word line and on a bit line and includes: a two-terminal non-volatile nanotube switching device having first and second terminals, a semiconductor diode element, and a nanotube fabric article capable of multiple resistance states. The semiconductor diode and nanotube article are between and in electrical communication with the first and second terminals, which are coupled to the word line bit line respectively. The operation circuit selects cells by activating bit and/or word lines, detects a resistance state of the nanotube fabric article of a selected memory cell, and adjusts electrical stimulus applied to the cell to controllably induce a selected resistance state in the nanotube fabric article. The selected resistance state corresponds to an informational state of the memory cell.
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Citations
32 Claims
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1. A memory array comprising:
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a plurality of word lines; a plurality of bit lines; a plurality of memory cells, each memory cell responsive to electrical stimulus on a word line and on a bit line, each memory cell including; a two-terminal non-volatile nanotube switching device comprising a first and a second terminal, a semiconductor diode element, and a nanotube fabric article, the semiconductor diode and a nanotube article disposed between and in electrical communication with the first and second terminals, wherein the nanotube fabric article is capable of a plurality of resistance states, and wherein the first terminal is coupled to the word line and the second terminal is coupled to the bit line, the electrical stimulus applied to the first and second terminals capable of changing the resistance state of the nanotube fabric article; and a memory operation circuit operably coupled to each bit line of the plurality of bit lines and each word line of the plurality of word lines, said operation circuit capable of selecting each of the cells by activating at least one of the bit line and the word line coupled to that cell to apply a selected electrical stimulus to each of the corresponding first and second terminals, said operation circuit further capable of detecting a resistance state of the nanotube fabric article of a selected memory cell and adjusting the electrical stimulus applied to each of the corresponding first and second terminals in response to the resistance state to controllably induce a selected resistance state in the nanotube fabric article; wherein the selected resistance state of the nanotube fabric article of each memory cell corresponds to an informational state of said memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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Specification