Semiconductor Memory Device

• US 20080212379A1
• Filed: 05/26/2006
• Published: 09/04/2008
• Est. Priority Date: 05/30/2005
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Asauchi, Noboru, Otsuka, Eitaro
• Granted Patent: US 7,499,372 B2
• Time in Patent Office: Days
• US Class Current: 365/189.07
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory

Abstract

When writing 16-bit write data to the memory array 100 which can store data of 8 bits per 1 row, the semiconductor memory device 10 first writes the upper 8 bits to the 1st write restricted row of the memory array 100. The increment controller 150 determines whether or not the value of the existing data written to the memory array 100 and the write data used for writing latched to the 8-bit latch register 170 match. When the existing data and the write data match, the increment controller 150 outputs the write enable signal WEN1 to the write/read controller 140 and executes the writing of the lower 8 bits of write data to the memory array 100.

Claims

1. A semiconductor memory device, comprising:

a sequentially accessed non-volatile memory array that has a plurality of data storage rows of a specified address unit;

write data holding module that holds write data of a data capacity correlating to n times (n is an integer of 2 or greater) the specified address unit in the specified address units, the data being the write data to be written to the memory array;

data writing module that writes in the specified address unit the held write data to the subject data storage row that is subject to writing in the memory array;

data verification module that determines whether or not the already written data of the specified address unit written to the subject data storage row and the write data of the specified address unit held in the write data holding module match; and

a control unit that, when the already written data and the write data do not match, does not execute writing of the remaining write data to the next data storage row of the subject data storage row using the data writing module.

2. A semiconductor memory device in accordance with claim 1, wherein

when the already written data and the write data match, the control unit executes writing of the write data to the next data storage row of the subject data storage row using the data writing module.

3. A semiconductor memory device in accordance with claim 1, wherein

the data verification module reads the already written data in the address units from the subject data storage row after writing of the write data to the subject data storage row has ended, and

using the already written data read in the specified address unit and the write data of the specified address unit, a determination is made of whether or not the already written data and the write data match.

4. A semiconductor memory device in accordance with claim 1, wherein

the data verification module, after writing of the write data to the subject data storage row has ended, reads the already written data for each 1 address from the subject data storage row and also fetches the write data in 1 address units from the write data holding module, and

using the already written data read in the specified 1 address unit and the fetched 1 address unit write data, a determination is made of whether or not the already written data and the write data match.

5. A semiconductor memory device in accordance with claim 1 further comprising

existing data holding module that holds existing data stored in the subject data storage row before the write data is written;

and

a data write back module that writes back the existing data held in the existing data holding module to the subject data storage row when it is determined by the data verification module that the already written data and the write data do not match.

6. A semiconductor memory device in accordance with claim 1, wherein

data is stored in the data storage row in sequence from the most significant bit, and

the data write module executes writing of the data in sequence from the most significant bit to the memory array.

26. A print recording material receptor that detachably mounted onto a printing device, the print recording material receptor comprising:

one or a plurality of print recording material receptor units to house print recording material, and

a semiconductor memory device in accordance with any of claims 1 to 8 and 15 to 19, the semiconductor memory device storing information related to the print recording material housed in the print recording material receptor units.

27. A printing system comprising a printing device and a print recording material receptor as set forth in claim 26, detachably mounted onto the printing device, wherein:

said printing device includes a host computer, wherein the host computer is connected to a semiconductor memory device of the print recording material receptor through a data signal line, a clock signal line, a reset signal line, a positive power supply line and a negative power supply line, and sends data of the quantity of the print recording material consumed in the printing device to the semiconductor memory device; and

said semiconductor memory device attached to said print recording material receptor stores, in said memory array, the quantity data regarding the print recording material that has been received.

7. A semiconductor memory device, comprising:

a sequentially accessed non-volatile memory array that has a plurality of data storage rows having 8 data cells that store 1 bit of data, respectively;

write data holding module that holds in 8-bit units write data to be written to the memory array, holding the write data in multiple n of 8 bits (n is an integer of 2 or greater);

data writing module that writes in 8-bit units the held write data to the subject data storage row that is the subject of writing to the memory array;

data verification module that determines whether or not the 8 bits of already written data written to the subject data storage row and the 8 bits of write data held in the write data holding module match; and

a control unit that, when the already written data and the write data do not match, does not execute writing of the remaining write data to the next data storage row of the subject data storage row.

8. A semiconductor memory device in accordance with claim 7, wherein

when the already written data and the write data do match, the control unit executes writing of the write data to the next data storage row of the subject data storage row using the data writing module.

9. A write control method of writing write data of a data capacity correlating to a multiple n (n is an integer of 2 or greater) of a specified address unit to a semiconductor memory device that has a sequentially accessed non-volatile memory array that has a plurality of data storage rows of a specified address unit, the method comprising:

receiving the write data of the data capacity correlating to n times the specified address unit;

holding in the specified address unit the received write data;

writing in the specified address unit the held write data to the subject data storage row that is subject to write in the memory array;

determining whether or not the already written data of the specified address unit written to the subject data storage row and the held write data of the specified address unit match; and

when the already written data and the write data do not match, not executing writing of the remaining write data to the next data storage row of the subject data storage row.

10. A write control method in accordance with claim 9, wherein

when the already written data and the write data match, executing the writing of write data of the address unit to the next data storage row of the subject data storage row.

11. A write control method in accordance with claim 10 further comprising:

determining whether or not the already written data of the specified address unit written to the next data storage row and the held write data of the specified address unit match; and

when the already written data and the write data do not match, not executing the writing of the remaining write data to the next data storage row of the next data storage row.

12. A write control method of writing write data of a multiple n of 8 bits (n is an integer of 2 or greater) to a semiconductor memory device that has a sequentially accessed non-volatile memory array that has a plurality of data storage rows having 8 data cells that store 1 bit of data, the method comprising:

receiving write data of a data length of the multiple n of 8 bits;

holding in 8-bit units the received write data;

writing in 8-bit units the held write data to the subject data storage row that is the subject of writing to the memory array;

determining whether or not the 8-bit unit already written data written to the subject data storage row and the held 8-bit unit write data match; and

when the already written data and the write data do not match, not executing the writing of the remaining write data to the next data storage row of the subject data storage row.

13. A write control method in accordance with claim 12, wherein

when the already written data and the write data match, executing the writing of the 8-bit unit write data to the next data storage row of the subject data storage row.

14. A write control method in accordance with claim 13 further comprising:

determining whether or not the 8-bit unit already written data written to the next data storage row and the held 8-bit unit write data match, and

when the already written data and the write data do not match, not executing the writing of the remaining write data to the next data storage row of the next data storage row.

15. A semiconductor memory device comprising:

a non-volatile memory array; and

a read/write controller that controls writing data to said memory array and reading data out of said memory array;

wherein,

said read/write controller, when a request of writing data to said memory array is received, compares the value of multibit write data that has been inputted to the value of multibit stored data that is stored in a multibit memory area to which said multibit write data is to be written, with said comparison being performed bitwise manner beginning with the largest bit of said multibit write data, then if for the value of each bit of said stored data there is a bit that is determined to fulfill a specific magnitude relationship, writes the write data for the bit that has been so determined, after which checks whether or not the stored data that has been stored in the memory area to which writing has been performed matches said write data for said bit that had been determined, if there is a match, writes the write data of a bit that is after said bit that had been determined, but if there is no match, prohibits the writing of the write data of all bits that are after said bit that had been determined.

17. A semiconductor memory device in accordance with claim 15 further comprising:

an address counter that outputs an incremented count value after the writing of the data for the determined bits to the memory array;

a subtractor that sets a read address to the memory array to a value of the incremented count value minus one; and

a data buffer latches the write data for the determined bit as a latch data;

wherein the read/write controller reads the stored data stored in the memory area to which writing has been performed by the read address set at the subtractor, compares the stored data with the latch data and then checks whether the stored data matches the latch data.

16. A semiconductor memory device comprising:

a non-volatile memory array; and

a read/write controller that controls writing data to said memory array and reading data out of said memory array;

wherein,

said read/write controller, when a request of writing data to said memory array is received, compares the value of multibit write data that has been inputted to the value of multibit stored data that is stored in a multibit memory area to which said multibit write data is to be written, with said comparison being performed bitwise manner beginning with the largest bit of said multibit write data, if for the value of each bit of said stored data there is a bit that is determined to fulfill a specific magnitude relationship, writes all at once for the write data for the n bits (where n is an integer of 2^m, where m is a positive integer) starting with said bit that has been so determined, after which checks whether or not the stored data that has been stored in the memory area to which writing has been performed matches said write data for said bits that had been determined, wherein, if there is a match, writes in n-bit units for the write data of bits starting n bits after said bits that had been determined, but if there is no match, prohibits the writing of the write data of bits starting n bits after said bit that had been determined.

18. A semiconductor memory device comprising.

a non-volatile memory array;

and

a read/write controller that controls writing data to said memory array and reading data out of said memory array;

wherein,

said read/write controller;

when a request to write data to said memory array is received, writes inputted multibit write data to a multibit memory area to which the inputted mulitbit write is to be written, and checks whether or not the stored data that has been stored in the memory area to which the writing was performed matches the inputted multibit write data, and if there is no match, then prohibits the writing of bits that are after said inputted multibit write data.

19. A semiconductor memory device comprising:

a non-volatile memory array; and

a read/write controller for controlling writing data to said memory array and reading data out of said memory array;

wherein,

said read/write controller;

when a request of writing data to said memory array is received, writes inputted n-bit (where n is an integer of 2^m, where m is a positive integer) write data to a multibit memory area to which the inputted n-bit write data is to be written; and

after said writing has been performed, checks whether or not the stored data that has been stored in the memory area to which the writing was performed matches the inputted n-bit write data, and if there is no match, then prohibits the writing of bits that are after said inputted n-bit write data.

20. A method of controlling writing in a semiconductor memory device having a non-volatile memory array, the method comprising:

receiving a request to write data to the memory array;

comparing the value of multibit write data to the value of multibit stored data in bitwise manner from the largest bit of the multibit write data, wherein the multibit write data is a data to be inputted, and wherein the value of multibit stored data is stored in a multibit memory area to which said multibit write data is to be written; and

if for the value of each bit of said stored data there is a bit that is determined to fulfill a specific magnitude relationship, writing the write data for the bit that has been so determined, after which checking whether or not the stored data that has been stored in the memory area to which writing has been performed matches said write data for said bit that had been determined, if there is a match, writing the write data of a bit that is after said bit that had been determined, but if there is no match, prohibiting the writing of the write data of all bits that are after said bit that had been determined.

21. A method of controlling writing in a semiconductor memory device having a non-volatile memory array, the method comprising:

receiving a request to write data to the memory array;

comparing the value of multibit write data to the value of multibit stored data in bitwise manner from the largest bit of the multibit write data, wherein the multibit write data is a data to be inputted, and wherein the value of multibit stored data is stored in a multibit memory area to which said multibit write data is to be written; and

if for the value of each bit of said stored data there is a bit that is determined to fulfill a specific magnitude relationship, writing all at once for the write data for the n bits (where n is an integer of 2^m, where m is a positive integer) starting with said bit that has been so determined, after which checking whether or not the stored data that has been stored in the memory area to which writing has been performed matches said write data for said bits that had been determined, if there is a match, writing, in n-bit units, the write data of bits starting n bits after said bits that had been determined, but if there is no match, prohibiting the writing of the write data of bits starting n bits after said bit that had been determined.

22. A method of controlling writing in a semiconductor memory device having a non-volatile memory array, the method comprising:

receiving a request to write data to the memory array;

writing inputted multibit write data to a multibit memory area to which said inputted mulitbit write data is to be written; and

after said writing, checking whether or not the stored data that has been stored in the memory area to which the writing was performed matches the inputted multibit write data, and if there is no match, then prohibiting the writing of bits that are after said inputted multibit write data.

23. A method of controlling writing in a semiconductor memory device having a non-volatile memory array, the method comprising:

receiving a request to write data to the memory array;

writing inputted n-bit (where n is an integer of 2^m, where m is a positive integer) write data is written to a multibit memory area to which said inputted n-bit write data is to be written; and

after said writing, checking whether or not the stored data that has been stored in the memory area to which the writing was performed matches the inputted n-bit write data, and if there is no match, then prohibiting the writing of bits that are after said inputted n-bit write data.

24. A computer readable medium storing a computer program that controls writing in a semiconductor memory device having a non-volatile memory array, wherein the computer program is implemented in a computer and implements:

function of receiving a request to write data to the memory array;

function of comparing the value of multibit write data to the value of multibit stored data in bitwise manner from the largest bit of the multibit write data, wherein the multibit write data is a data to be inputted, and wherein the value of multibit stored data is stored in a multibit memory area to which said multibit write data is to be written; and

if for the value of each bit of said stored data there is a bit that is determined to fulfill a specific magnitude relationship, function of writing the write data for the bit that has been so determined, after which function of checking whether or not the stored data that has been stored in the memory area to which writing has been performed matches said write data for said bit that had been determined, if there is a match, function of writing the write data of a bit that is after said bit that had been determined, but if there is no match, function of prohibiting the writing of the write data of all bits that are after said bit that had been determined.

25. A computer readable medium storing a computer program that controls writing in a semiconductor memory device having a non-volatile memory array, wherein the computer program is implemented in a computer and implements:

function of receiving a request to write data to the memory array;

function of comparing the value of multibit write data to the value of multibit stored data in bitwise manner from the largest bit of the multibit write data, wherein the multibit write data is a data to be inputted, and wherein the value of multibit stored data is stored in a multibit memory area to which said multibit write data is to be written; and

if for the value of each bit of said stored data there is a bit that is determined to fulfill a specific magnitude relationship, function of writing all at once for the write data for the n bits (where n is an integer of 2^m, where m is a positive integer) starting with said bit that has been so determined, after which function of checking whether or not the stored data that has been stored in the memory area to which writing has been performed matches said write data for said bits that had been determined, if there is a match, function of writing, in n-bit units, the write data of bits starting n bits after said bits that had been determined, but if there is no match, function of prohibiting the writing of the write data of bits starting n bits after said bit that had been determined.