CHIP CIRCUIT FOR COMBINED AND DATA COMPRESSED FIFO ARBITRATION FOR A NON-BLOCKING SWITCH
First Claim
1. A chip circuit for use in data packet switching in which a buffer is used for buffering input control information about incoming packets at a plurality of m input ports to be switched to a plurality of n output ports of a respective switching device, and being enabled for concurrent read operation from at least a subtotal of output ports, the chip circuit comprising:
- a.) a compressing circuit compressing said input control information from an indicator bit vector, an indicator bit representing either information data present or data absent on a respective one of said data input ports,b.) a storing circuit storing respective subsets of said compressed control information according to an output port indication evaluated from packet header information into a respective buffer storage provided per output port, andc.) an evaluating circuit evaluating the compressed control information from the total of buffer storages for switching the respective data packet to the desired switching device output port,said compressing circuit further comprising an input port subgroup index circuit building an input port subgroup index addressing respective subgroups of the total of input ports, each subgroup covering a predetermined plurality of input ports, anda subgroup indication indicating each subgroup for tracking at which input ports of a subgroup data is concurrently present.
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Abstract
A system for switching data packets through a multiple (m) input, multiple (n) output switching device providing switching having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped.
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Citations
10 Claims
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1. A chip circuit for use in data packet switching in which a buffer is used for buffering input control information about incoming packets at a plurality of m input ports to be switched to a plurality of n output ports of a respective switching device, and being enabled for concurrent read operation from at least a subtotal of output ports, the chip circuit comprising:
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a.) a compressing circuit compressing said input control information from an indicator bit vector, an indicator bit representing either information data present or data absent on a respective one of said data input ports, b.) a storing circuit storing respective subsets of said compressed control information according to an output port indication evaluated from packet header information into a respective buffer storage provided per output port, and c.) an evaluating circuit evaluating the compressed control information from the total of buffer storages for switching the respective data packet to the desired switching device output port, said compressing circuit further comprising an input port subgroup index circuit building an input port subgroup index addressing respective subgroups of the total of input ports, each subgroup covering a predetermined plurality of input ports, and a subgroup indication indicating each subgroup for tracking at which input ports of a subgroup data is concurrently present. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification