VIDEO ENCODING AND VIDEO/AUDIO/DATA MULTIPLEXING DEVICE

• US 20080212681A1
• Filed: 05/13/2008
• Published: 09/04/2008
• Est. Priority Date: 04/06/1999
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Yavits, Leonid, Morad, Amir
• Granted Patent: US 7,751,480 B2
• Time in Patent Office: Days
• US Class Current: 375/240.16
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/43 Hardware specially adapted for motion estimation or compensation
• CPC Class Codes: H04N 19/436 using parallelised computational arrangements
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

The present invention provides a buffer architecture and latency reduction mechanism for buffering uncompressed/compressed information. This combination provides for a proficient division of the encoding task and quicker through-put time. The invention teaches a single chip digital signal processing device for real time video/audio compression comprising a plurality of processors, including a video input processor, a motion estimation processor, a digital signal processor, and a bitstream processor, wherein processing and transfer of the signals within the device is done in a macroblock-by-macroblock manner. The device can include a multiplexing processor that is comprised of a storage unit which buffers a compressed video bitstream and a processor which retrieves the compressed video bitstream from the storage unit and produces a multiplexed data stream whereby the compressed video bitstream is processed in a pipeline manner.

Claims

1. A single chip digital signal processing device for real time video/audio compression, said device comprising:

a plurality of processors, wherein said plurality of processor comprises;

a video input processor which receives, analyzes, scales and processes a digital signal,

a motion estimation processor which receives said processed signal, produces a motion analysis therefrom;

a digital signal processor which receives said processed signal, and according to said motion analysis, compresses said processed signal and produces a compressed processed signal, and;

a bitstream processor which receives and formats said compressed processed signal;

wherein processing and transfer of said signals within said device is done in a macroblock-by-macroblock manner, thus enabling pipeline macroblock-by-macroblock processing.

2. A device according to claim 1, further comprising:

a memory controller connected to said plurality of processors, wherein said memory controller controls data communication among said digital signal processor, said motion estimation processor, said video input processor and an external storage unit.

3. A device according to claim 1, wherein said plurality of processors further comprises:

a multiplexing processor which multiplexes plurality of digital signals and produces a multiplexed stream.

4. A device according to claim 3, further comprising:

a global controller which controls and schedules said video input processor, said motion estimation processor, said digital signal processor, said bitstream processor, said multiplexing processor and said memory controller.

5. A device according to claim 3, wherein said motion estimation processor, said digital signal processor, said video input processor, said bitstream processor and said multiplexing processor operate in parallel.

6. A device according to claim 3, wherein said motion estimation processor operates on macroblock a of frame I, said digital signal processor operates on macroblock b of frame I, said bitstream processor operates on macroblock c of frame I, said multiplexing processor operates on frame J, wherein a≧

b≧

c, and I≧

J.

7. A device according to claim 1, wherein said video input processor comprises:

a capture unit which acquires a multiple frame video signal;

a video storage which buffers said multiple frame video signal thereby allowing adjustment between an internal video rate and an external data communication rate;

a pre-encoding processor which receives said multiple frame video signal from said capture unit and produces statistical analysis of said multiple frame video signal;

a scaler which receives said multiple frame video signal from said pre-encoding processor and modifies picture resolution;

a video processor which processes said multiple video signal, and;

a controller which controls and schedules said capture unit, said pre-encoding processor, said scaler, said video processor and said video storage.

9. A device according to claim 7, further comprising:

an input storage unit which buffers said multiple frame video signal, thereby adjusting between external communication rate and internal video rate.

10. A device according to claim 6, wherein said video input processor operates on frame K such that K≧

I≧

J.

11. A device according to claim 3, wherein said multiplexing processor comprises:

a first video storage which buffers a compressed video bitstream, and which transfers said compressed video bitstream to said external memory unit, thereby adjusting between internal multiplexor processing rate and external communication rate;

a second video storage which reads from said memory unit said compressed video bitstream, and which buffers said compressed video bitstream, thereby adjusting between said external communication rate and said multiplexor processing rate;

an audio/data storage which buffers said digitized audio/data signal and which transfers said digitized audio/data signal to said processor, thereby adjusting between said external audio rate and said multiplexor processing rate;

a processor connected to said first and second video storage, said audio/data storage and said output storage, and which produces a multiplexed video/audio data stream, and;

an output storage which buffers said multiplexed video/audio/data stream, thereby adjusting between multiplexed video/audio/data stream rate and external communication rate.

8. A device according to claim 8, wherein said multiple frame video signal is acquired from at least one of the following:

a video interface and a host interface.

12. A video compression system comprising:

a host interface;

a memory unit and;

a digital signal processing device which receives a multiplicity of signals from said host interface and said memory unit and produces a multiplexed encoded data stream.

13. A system according to claim 12, wherein said multiplicity of signals comprises at least one of the following, a video signal, an audio signal, and a user data stream.

14. A system according to claim 12, further comprising:

a video interface which supplies a video signal to said digital signal processing device.

15. A system according to claim 12, further comprising:

a compressed data interface which receives said encoded signal from said digital signal processing device.

16. A system according to claim 12, further comprising:

an audio interface which transfers a digitized audio/user data signal to said digital signal processing device.

17. A system according to claim 12, wherein said device comprises:

a plurality of processors, wherein said plurality of processor comprises at least the following;

a digital signal processor which processes a digital signal and produces a processed signal;

a bitstream processor which receives and formats said processed signal; and

a motion estimation processor which receives said digital signal, produces a motion analysis therefrom, and transfers said motion analysis to said digital signal processor, which produces said processed signal according to said motion analysis.

18. A system according to claim 17, wherein said plurality of processors comprises a video input processor which receives, analyzes, scales and processes said digital signal.

19. A system according to claim 17, said device further comprising:

a memory controller connected to said plurality of processors, wherein said memory controller controls data communication among said digital signal processor, said motion estimation processor, said video input processor and an external storage unit.

20. A system according to claim 17, and wherein said plurality of processors comprises a multiplexing processor which multiplexes a plurality of digital signals and produces a multiplexed stream.

21. A system according to claim 17, said device further comprising:

a global controller which controls and schedules said video input processor, said motion estimation processor, said digital signal processor, said bitstream processor, said multiplexing processor and said memory controller.

22. A video input processor comprising:

a capture unit which acquires a multiple frame video signal, and;

a video storage which buffers said multiple frame video signal in a pipeline manner thereby adjusting between an external video rate and an internal data communication rate.

23. A video input processor according to claim 22, further comprising:

a pre-encoding processor which receives said multiple frame video signal from said capture unit and produces statistical analysis of said multiple frame video signal.

24. A video input processor according to claim 23, further comprising:

a scaler which receives said multiple frame video signal from said pre-encoding processor and modifies picture resolution.

25. A video input processor according to claim 24, further comprising:

a video processor which processes said multiple frame video signal.

26. A video input processor according to claim 25, further comprising:

a controller which controls and schedules said capture unit, said pre-encoding processor, said scaler, said video processor and said video storage.

27. A multiplexing processor comprising:

a storage unit which buffers a compressed video bitstream, thereby adjusting between an external communication rate and an internal compressed video bitstream rate, and;

a processor which retrieves said compressed video bitstream from said storage unit and produces a multiplexed data stream;

whereby said compressed video bitstream is processed in a pipeline manner.

35. A multiplexing processor according to claim 27, wherein said multiplexing processor interfaces directly with a variety of communication devices, each said variety of communication devices having a different communication speed.

36. A multiplexing processor according to claim 35, wherein said variety of communication devices are one of the following:

a computer bus, and an asynchronous transmission line.

28. A multiplexing processor comprising

a plurality of storage units, wherein said plurality of storage units comprises at least one of the following:

a first storage unit which buffers a compressed video bitstream and transfers said compressed video bitstream to an external memory unit, thereby adjusting between an internal compressed video bitstream rate and an external communication rate,

a second storage unit which receives said compressed video bitstream from said external memory unit and buffers said compressed video bitstream, thereby adjusting between said external memory communication rate and an internal multiplexor processing rate, and;

a processor which retrieves said compressed video bitstream from said second storage unit and produces a multiplexed data stream.

whereby said compressed video bitstream is processed in a pipeline manner.

29. A multiplexing processor according to claim 28 and wherein said plurality of storage units comprises:

a third storage which buffers a digitized audio/user data signal and transfers it to said processor, thereby adjusting between said digitized audio/data rate and said internal multiplexor processing rate.

30. A multiplexing processor according to claim 29, wherein said plurality of storage units comprises:

a fourth storage unit which buffers said multiplexed data stream and transfers it to an external receiving unit, thereby adjusting between said internal multiplexor processing rate and an external receiving device communication rate.

31. A multiplexing processor according to claim 28, wherein said first video storage is connected to an external memory controller, wherein said multiplexing processor buffers said compressed video bitstream in a real time variable rate and said external memory controller transfers said compressed video bitstream in a burst to said external memory unit.

32. A multiplexing processor according to claim 28, wherein said second video storage transfers said compressed video bitstream in a real time variable rate to said processor, and wherein said external memory unit transfers said compressed video bitstream in a burst to said second video storage.

33. A multiplexing processor according to claim 29, wherein said third storage is connected to an external audio source, wherein said third storage transfers said digitized audio/data signal to said processor in a real time variable rate and said external audio source transfers said digitized audio/data signal in a burst to said third storage.

34. A multiplexing processor according to claim 28, wherein said external memory unit acts as a temporary video buffer, thereby accumulating compressed video bitstream when said processor is unable to accept said compressed video bitstream.

37. A method for encoding, comprising the steps of:

capturing a pipeline of a multiplicity of digitized video frames; and

encoding said multiple digitized video frames, one macroblock at a time.