METHOD AND APPARATUS FOR GENERATING CLOCKS FOR A HANDHELD MULTISTANDARD COMMUNICATION SYSTEM

• US 20080212728A1
• Filed: 04/07/2008
• Published: 09/04/2008
• Est. Priority Date: 03/14/2005
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Paul Y. Lu
• Inventors: Lu, Paul Y.
• Granted Patent: US 7,801,558 B2
• Time in Patent Office: Days
• US Class Current: 375/356
• CPC Class Codes: H04B 1/1615 Switching on; Switching off, e.g. remotely battery saving circuits associated with selective call operation H04W52/00; details of power consumption reduction in a PLL, H03L7/0802, H03L7/14, H03L2207/08, H03L2207/18; muting amplifiers by gain control see H03G3/34
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04W 52/029 reducing the clock frequency of the controller
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

Systems and methods for processing signals are disclosed. The method may include, in a communication system comprising a plurality of devices, controlling the supply of one or more clock signals from a first clock source to one or more of the plurality of devices based on a signal communicated from a particular one of the plurality of devices to a second clock source and a request for a clock signal from one of the plurality of devices. The communicated signal may control an accuracy of the second clock source. The particular one of the plurality of devices may have highest accuracy requirements among the plurality of devices. At least one main clock signal may be generated for at least one of the plurality of devices utilizing an input clock signal received from the second clock source.

Claims

1-20. -20. (canceled)

21. A method for processing signals, the method comprising:

in a communication system comprising a plurality of devices, controlling the supply of one or more clock signals from a first clock source to one or more of said plurality of devices based on;

a signal communicated from a particular one of said plurality of devices to a second clock source, wherein said communicated signal controls an accuracy of said second clock source; and

a request for a clock signal from one of said plurality of devices.

22. The method according to claim 21, wherein said particular one of said plurality of devices has highest accuracy requirements among said plurality of devices.

23. The method according to claim 21, comprising generating at least one main clock signal for at least one of said plurality of devices utilizing an input clock signal received from said second clock source.

24. The method according to claim 23, comprising supplying said generated at least one main clock signal to said at least one of said plurality of devices within said communication system in response to receiving said request for said clock signal.

25. The method according to claim 21, comprising generating a real-time clock signal for low-power mode operation of said plurality of devices.

26. The method according to claim 25, comprising generating said real-time clock signal for said plurality of devices by a real-time clock signal source.

27. The method according to claim 26, comprising supplying said generated real-time clock signal to each of said plurality of devices.

28. The method according to claim 23, comprising, if said generated at least one main clock signal is ready for use, asserting at least one READY signal.

29. The method according to claim 24, comprising receiving at least one clock request signal that controls said supplying of said generated at least one main clock signal to said at least one of said plurality of devices.

30. The method according to claim 29, wherein said received at least one clock request signal comprises one or both of a clock ON command and/or a clock OFF command.

31. The method according to claim 23, comprising, if said at least one of said plurality of devices communicates a clock ON command, supplying said generated at least one main clock signal to said at least one of said plurality of devices.

32. The method according to claim 23, comprising, if each of said plurality of devices communicates a clock OFF command, disabling said generation of said at least one main clock signal.

33. A system for processing signals, the system comprising:

at least one circuitry in a communication system comprising a plurality of devices, said at least one circuitry controls the supply of one or more clock signals from a first clock source to one or more of said plurality of devices based on;

a signal communicated from a particular one of said plurality of devices to a second clock source, wherein said communicated signal controls an accuracy of said second clock source; and

a request for a clock signal from one of said plurality of devices.

34. The system according to claim 33, wherein said particular one of said plurality of devices has highest accuracy requirements among said plurality of devices.

35. The system according to claim 33, wherein said at least one circuitry generates at least one main clock signal for at least one of said plurality of devices utilizing an input clock signal received from said second clock source.

36. The system according to claim 35, wherein said at least one circuitry supplies said generated at least one main clock signal to said at least one of said plurality of devices within said communication system in response to receiving said request for said clock signal.

37. The system according to claim 33, wherein said at least one circuitry generates a real-time clock signal for low-power mode operation of said plurality of devices.

38. The system according to claim 37, wherein said at least one circuitry generates said real-time clock signal for said plurality of devices by a real-time clock signal source.

39. The system according to claim 38, wherein said at least one circuitry supplies said generated real-time clock signal to each of said plurality of devices.

40. The system according to claim 35, wherein said at least one circuitry asserts at least one READY signal, if said generated at least one main clock signal is ready for use.

41. The system according to claim 36, wherein said at least one circuitry receives at least one clock request signal that controls said supplying of said generated at least one main clock signal to said at least one of said plurality of devices.

42. The system according to claim 41, wherein said received at least one clock request signal comprises one or both of a clock ON command and/or a clock OFF command.

43. The system according to claim 35, wherein said at least one circuitry supplies said generated at least one main clock signal to said at least one of said plurality of devices, if said at least one of said plurality of devices communicates a clock ON command.

44. The system according to claim 35, wherein said at least one circuitry disables said generation of said at least one main clock signal, if each of said plurality of devices communicates a clock OFF command.