PLL/DLL dual loop data synchronization

• US 20080212730A1
• Filed: 03/14/2008
• Published: 09/04/2008
• Est. Priority Date: 12/20/2000
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Tang, Benjamim, Southwell, Scott, Steffen, Nicholas
• Granted Patent: US 7,743,168 B2
• Time in Patent Office: Days
• US Class Current: 375/376
• CPC Class Codes: H04J 3/047 Distributors with transistors or integrated circuits
• CPC Class Codes: H04J 3/062 Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers pulse-stuffing H04J3/07; asynchronous-synchronous conversion H04L5/24; speed conversion H04L25/05; speed conversion in computers G06F5/06
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL instead of the local reference. Thus, the DLL adjusts the frequency from the PLL so that it matches the desired data rate. Each loop may be optimized for jitter tolerance with the net effect generating a synthesized clean clock (due to narrow bandwidth filtering) and VCO noise suppression (due to wide bandwidth filtering). A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.

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23. A plesiochrononous data retiming method comprising:

recovering a clock from a received serial input data at a digital delay locked loop (DDLL);

deserializing said serial data to a parallel data using said recovered clock;

writing said parallel data to a FIFO (first-in first-out);

synthesizing a transmit clock;

reading said parallel data from said FIFO;

serializing said parallel data using said synthesized transmit clock;

detecting a FIFO fill level at a delay locked loop (DLL); and

phase shifting, in a phase lock loop (PLL), an output of a VCO, wherein said phase shifting is in response to said detecting step.

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36. In a plesiochronous system, a dual loop data serializer comprising:

a first-in-first-out (FIFO) register, having a fill rate, and receiving a parallel data input and a data clock input and providing a plurality of outputs;

a parallel-in serial-out (PISO) serializer having an input coupled to one of the plurality of outputs of said FIFO register;

for receiving an input signal from said FIFO register, and outputting serialized data;

a phase detector, having at least one input coupled to at least one of the plurality of outputs of said FIFO register, for receiving a signal representative of the fill rate of said FIFO register, said phase detector having an output for providing an output signal;

a narrow band loop filter coupled between said output of said phase detector and a phase shifter and configured to provide an output to a phase shifter, thereby producing a phase shift in a PLL;

the phase shifter having a first input adapted to receive the output signal from said narrow band loop filter and providing an output signal to a phase/frequency detector;

the phase/frequency detector having an input for receiving the output signal from said phase shifter and also receiving a local reference input, and providing an output signal to a wideband loop filter;

the wideband loop filter having an input for receiving the output signal from the phase/frequency detector to suppress phase noise and adapted to provide an output signal to a voltage controlled oscillator (VCO);

the voltage controlled oscillator (VCO) having an input adapted to receive the output signal from said wideband loop filter, and adapted to provide a synthesized clock output signal to said PISO serializer and also to a second input of said phase shifter;

said phase shifter, phase/frequency detector, and wideband loop filter forming a phase locked loop with the VCO, such that the phase and frequency of the synthesized clock output signal of the VCO is modified by the output signal from the narrow band loop filter; and

said PISO serializer providing the synthesized clock signal to said FIFO register;

whereby said phase detector compares the data clock with the synthesized clock signal.

37. In a plesiochronous system, a dual loop data serializer, as in claim 36, and further comprising:

a digital delay lock loop (DDLL) receiving an input data signal to be retimed and configured to recover a clock of said input data signal, said DDLL providing an output to a decision circuit;

the decision circuit receiving the output of said DDLL and also receiving said input data signal; and

a serial-in and parallel-out (SIPO) deserializer coupled between said decision circuit and said first-in first-out (FIFO) register for providing a parallel data input to said first-in first-out (FIFO) register.

The data serializer of claim 36, wherein said PLL locks to said signal from said FIFO to said phase detector.

38. The data serializer of claim 36, wherein said wideband loop filter of said PLL comprises a wideband analog filter to suppress VCO phase noise and generate a low jitter clock.

39. The data serializer of claim 36, wherein said narrow band loop filter of said DLL comprises a digital narrow band filter to filter noise from the data clock and set the jitter bandwidth.

40. The data serializer of claim 36, wherein said signal representative of the fill rate of said FIFO register and inputted to said phase detector comprises a FIFO fill level indicator.

41. The data serializer of claim 40, wherein said phase detector is configured to translate said FIFO fill level into a digital value.

42. A dual loop retimer comprising the data serializer of claim 36.

54. The data serializer of claim 36 wherein said PLL locks to said signal from said FIFO to said phase detector.

43. In a plesiochronous system, a method for PLL/DLL data serialization comprising:

detecting a local reference at a phase/frequency detector (PFD) of a phase lock loop (PLL);

phase locking a voltage controlled oscillator (VCO) of said PLL to a local reference to suppress a phase noise of said VCO;

receiving a parallel data input and a data clock at a FIFO register;

filtering, at a delayed lock loop (DLL), a signal representative of a fill level of said FIFO;

phase shifting an output of said VCO of said PLL in response to said filtering step;

locking said PLL to a frequency corresponding to a pre-filtered signal input to said DLL;

receiving, at a parallel-in serial-out (PISO) serializer, said parallel data and said VCO output; and

outputting a serialized data from said PISO serializer with said VCO outputting a transmit clock.

44. The method of claim 43, further comprising the step of outputting a synthesized clock.

45. The method of claim 43, wherein said PLL filtering step comprises wide bandwidth filtering.

46. The method of claim 43, wherein said DLL filtering step comprises narrow bandwidth filtering.

47. The method of claim 43, further comprising the step of translating said signal in said DLL to a digital value.

48. The method of claim 47, wherein said translating step comprises a phase detector in said DLL.

49. A plesiochronous data retimer comprising:

a digital delay lock loop (DDLL) receiving an input data to be retimed and configured to recover a clock of said input data;

a phase/frequency detector (PFD) receiving a local reference;

a phase shifter configured in a feedback loop with said PFD;

a first loop filter coupled to said phase shifter;

said phase/frequency detector (PFD), phase shifter and first loop filter forming a phase locked loop,

a serial-in and parallel-out (SIPO) deserializer coupled to said input data;

a first-in first-out FIFO register coupled to said deserializer; and

a parallel-in serial-out (PISO) serializer receiving said deserialized input data and transmitting a serialized data.

50. The retimer of claim 49, wherein said DDLL comprises a phase detector and a digital loop filter.

51. The retimer of claim 49, wherein said DDLL comprises a wide bandwidth.

52. The retimer of claim 49, further comprising a second loop filter.

53. The retimer of claim 51, further comprising a dual bandwidth.