METHOD OF FABRICATING SEMICONDUCTOR WAFER

• US 20080213982A1
• Filed: 02/28/2008
• Published: 09/04/2008
• Est. Priority Date: 03/02/2007
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Young-Soo, Lim, Young-Sam, Kim, Gi-Jung, Kim, Young-Nam, Choi, Joon-Young, Bae, Dae-Lok
• Application Number:
  US12/039,106
• Publication Number:
  US 20080213982A1
• Time in Patent Office: Days
• US Class Current: 438/480
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Abstract

Provided is a method of fabricating a semiconductor wafer. The method includes preparing a substrate wafer having a non-single-crystalline thin layer; disposing at least one single crystalline pattern adjacent to the non-single-crystalline thin layer on the substrate wafer; and forming a material layer contacting the single crystalline pattern on the non-single-crystalline thin layer.

Claims

1. A method of fabricating a wafer comprising:

preparing a substrate wafer having a non-single-crystalline thin layer;

disposing at least one single crystalline pattern adjacent to the non-single-crystalline thin layer on the substrate wafer; and

forming a material layer contacting the single crystalline pattern on the non-single-crystalline thin layer.

2. The method according to claim 1, wherein disposing the single crystalline pattern adjacent to the non-single-crystalline thin layer comprises:

coating a raw material containing a mixture of a carrier solution and a plurality of single crystalline semiconductor patterns on the non-single-crystalline thin layer; and

selectively removing the carrier solution to leave the single-crystalline semiconductor patterns on the non-single-crystalline thin layer.

3. The method according to claim 1, wherein the single crystalline pattern is one of polyhedrons having each side with a length of 1 mm to 5 cm,

wherein disposing the single crystalline pattern adjacent to the non-single-crystalline thin layer comprises disposing the single crystalline pattern on the non-single-crystalline thin layer using a mechanical transfer unit.

4. The method according to claim 1, wherein disposing the single crystalline pattern adjacent to the non-single-crystalline thin layer and forming the material layer comprises:

preparing a subsidiary wafer having at least one single crystalline pattern;

disposing the subsidiary wafer on the substrate wafer such that a top surface of the single crystalline pattern is disposed adjacent to a top surface of the non-single-crystalline thin layer;

forming the material layer contacting at least a portion of the single crystalline pattern on the non-single-crystalline thin layer; and

separating the subsidiary wafer from the substrate wafer to leave a portion of the single crystalline pattern on the substrate wafer.

5. The method according to claim 4, wherein forming the material layer contacting at least the portion of the single crystalline pattern is performed before separating the subsidiary wafer from the substrate wafer to leave the portion of the single crystalline pattern on the substrate wafer.

6. The method according to claim 4, wherein forming the material layer contacting at least the portion of the single crystalline pattern is performed after separating the subsidiary wafer from the substrate wafer to leave the portion of the single crystalline pattern on the substrate wafer,

wherein the single crystalline pattern is left in a mesh shape on the substrate wafer, and the material layer covers the single crystalline pattern left on the substrate wafer.

7. The method according to claim 4, wherein preparing the subsidiary wafer comprises forming at least one separation layer,

wherein separating the subsidiary wafer from the substrate wafer comprises defining the single crystalline pattern left on the substrate wafer by the separation layer.

8. The method according to claim 7, wherein preparing the subsidiary wafer having at least one single crystalline pattern comprises forming a deposition preventing pattern on the subsidiary wafer to expose an upper region of the single crystalline pattern.

9. The method according to claim 8, wherein the deposition preventing pattern covers a sidewall of the single crystalline pattern disposed under the separation layer and exposes a sidewall and top surface of the single crystalline pattern disposed on the separation layer.

10. The method according to claim 8, wherein the deposition preventing pattern is formed of at least one of a silicon nitride layer, a silicon oxide layer, and an organic layer.

11. The method according to claim 4, wherein the subsidiary wafer and the substrate wafer are single crystalline wafers, the non-single-crystalline thin layer is an insulating layer, and the portion of the single crystalline pattern left on the substrate wafer by separating the subsidiary wafer from the substrate wafer is a single crystalline semiconductor.

12. The method according to claim 11, wherein the subsidiary wafer differs from the substrate wafer in at least one of top-surface crystalline direction, material kind, and crystalline structure.

13. The method according to claim 4, after separating the subsidiary wafer from the substrate wafer, further comprising single-crystallizing the material layer using the portion of the single crystalline pattern left on the substrate wafer as a seed layer.

14. The method according to claim 4, wherein disposing the subsidiary wafer on the substrate wafer is performed such that a distance between the single crystalline pattern and the non-single-crystalline thin layer ranges from about 1A to about 10 mm.

15. The method according to claim 3, wherein preparing the substrate wafer comprises forming grooves in the non-single-crystalline thin layer in positions corresponding to the single crystalline patterns,

wherein disposing the subsidiary wafer on the substrate wafer comprises inserting the single crystalline patterns into the grooves.

16. The method according to claim 1, wherein forming the material layer comprises forming at least one of insulating layers and amorphous silicon (a-Si) or polycrystalline silicon (poly-Si) layers using a vapor deposition technique.

17. A method of fabricating a wafer comprising:

preparing a first wafer having at least one single crystalline pattern;

preparing a second wafer having a non-single-crystalline thin layer;

disposing the first wafer on the second wafer such that a top surface of the single crystalline pattern is disposed adjacent to a top surface of the non-single-crystalline thin layer;

forming a material layer contacting at least a portion of the single crystalline pattern on the non-single-crystalline thin layer; and

separating the first wafer from the second wafer to leave a portion of the single crystalline pattern on the second wafer.

18. The method according to claim 17, wherein forming the material layer contacting at least the portion of the single crystalline pattern is performed before separating the first wafer from the second wafer.

19. The method according to claim 17, wherein forming the material layer contacting at least the portion of the single crystalline pattern is performed after separating the first wafer from the second wafer,

wherein the single crystalline pattern is left in a mesh shape on the second wafer, and the material layer is formed to cover the single crystalline pattern left one the second wafer.

20. The method according to claim 17, wherein preparing the first wafer comprises forming at least one separation layer,

wherein separating the first wafer from the second wafer comprises defining the single crystalline pattern left on the second wafer by the separation layer.

21. The method according to claim 20, wherein forming the separation layer comprises implanting impurity ions into the first wafer.

22. The method according to claim 21, wherein the impurity ions constituting the separation layer contain hydrogen ions.

23. The method according to claim 21, wherein implanting impurity ions into the first wafer comprises performing ion implantation processes at least twice under different ion energy conditions such that the first wafer includes a plurality of separation layers formed at respectively different depths.

24. The method according to claim 20, wherein preparing the first wafer having at least one single crystalline pattern further comprises forming a deposition preventing pattern on the first wafer to expose an upper region of the single crystalline pattern.

25. The method according to claim 24, wherein the deposition preventing pattern covers a sidewall of the single crystalline pattern disposed under the separation layer and exposes a sidewall and top surface of the single crystalline pattern disposed on the separation layer.

26. The method according to claim 25, wherein forming the deposition preventing pattern comprises:

forming a deposition preventing layer on the first wafer having the single crystalline pattern;

forming a sacrificial layer on the deposition preventing layer;

etching back the sacrificial layer to expose the deposition preventing layer over the separation layer;

etching the exposed deposition preventing layer to form a deposition preventing pattern exposing the single crystalline pattern over the separation layer; and

removing the sacrificial layer to expose the deposition preventing pattern.

27. The method according to claim 24, wherein the deposition preventing pattern is formed of at least one of a silicon nitride layer, a silicon oxide layer, and an organic layer.

28. The method according to claim 17, wherein the first and second wafers are single crystalline wafers, the non-single-crystalline thin layer is an insulating layer, and the portion of the single crystalline pattern left on the second wafer by separating the first wafer from the second wafer is a single crystalline semiconductor.

29. The method according to claim 28, wherein the first wafer differs from the second wafer in at least one of top-surface crystalline direction, material kind, and crystalline structure.

30. The method according to claim 17, after separating the first wafer from the second wafer, further comprising single-crystallizing the material layer using the portion of the single crystalline pattern left on the second wafer as a seed layer.

31. The method according to claim 30, wherein single-crystallizing the material layer is performed using at least one of a thermal treatment technique and a laser annealing technique.

32. The method according to claim 17, after separating the first wafer from the second wafer, further comprising planarizing a top surface of the portion of the single crystalline pattern left on the second wafer and a top surface of the material layer.

33. The method according to claim 17, wherein disposing the first wafer on the second wafer is performed such that a distance between the single crystalline pattern and the non-single-crystalline thin layer ranges from about IA to about 10 mm.

34. The method according to claim 17, wherein preparing the second wafer comprises forming grooves in the non-single-crystalline thin layer in positions corresponding to the single crystalline patterns,

wherein disposing the first wafer on the second wafer comprises inserting the single crystalline patterns into the grooves.

35. The method according to claim 17, wherein forming the material layer comprises forming at least one of insulating layers and a-Si or poly-Si layers using a vapor deposition technique.

36. The method according to claim 17, wherein preparing the first wafer having at least one single crystalline pattern comprises:

forming at least one mask pattern on the first wafer;

patterning the first wafer using the mask pattern as an etch mask to form the at least one single crystalline pattern; and

removing the mask pattern to expose a top surface of the single crystalline pattern,

wherein each shape of the mask pattern and the single crystalline pattern is one of a polygon and a circular shape from a plan view parallel to the top surface of the first wafer.