Method for manufacturing semiconductor device

• US 20080213983A1
• Filed: 02/28/2008
• Published: 09/04/2008
• Est. Priority Date: 03/02/2007
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Taguwa, Tetsuya
• Granted Patent: US 7,563,698 B2
• Time in Patent Office: Days
• US Class Current: 438/486
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

Method for manufacturing a semiconductor device including a transistor having a grooved gate structure and a transistor having a planar gate structure on the same substrate, in which, even when the semiconductor device is configured as a dual gate structure in which a gate electrode structure is a poly-metal gate structure, and a grooved gate and a planar gate are made in different conductivity types, then sufficient dopant is injected into polysilicon in the grooved gate to prevent depletion, and impurity ions do not pass through a gate insulating film even when the planar gate is formed also polysilicon having the same film thickness. The method includes: injecting ions into an amorphous silicon layer for the grooved gate; subsequently, turning it into polysilicon once; injecting ions once again to amorphousize a surface layer of the polysilicon layer and injecting ions of a different conductivity type for the planar gate.

Claims

1. A method for manufacturing a semiconductor device including both of a grooved gate transistor and a planar gate transistor on a same semiconductor substrate, the method comprises:

(a) forming a groove in the semiconductor substrate in the forming region of the grooved gate transistor,

(b) filling the groove provided in the semiconductor substrate in the forming region of the grooved gate transistor to form an amorphous silicon layer on the entire surface,

(c) ion injecting an impurity of a first conductivity type into the amorphous silicon layer in the forming region of the grooved gate transistor,

(d) entirely heating the semiconductor substrate to convert the amorphous silicon layer to a polysilicon layer,

(e) amorphousizing a surface layer of the polysilicon layer, and

(f) ion injecting an impurity of a second conductivity type into the amorphousized surface layer and the polysilicon layer in the forming region of the planar gate transistor.

2. The method for manufacturing a semiconductor device according to claim 1, wherein, before the step (a), the method further comprises forming an element isolation insulating film for separating the forming region of the grooved gate transistor from the forming region of the planar gate transistor in the semiconductor substrate.

3. The method for manufacturing a semiconductor device according to claim 1, wherein, between the steps (a) and (b), the method further comprises forming a gate insulating film on the entire surface of the semiconductor substrate.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the step (e) amorphousizing a surface layer of the polysilicon layer is carried out by ion injecting an impurity of the first conductivity type into the entire surface of the polysilicon layer.

5. The method for manufacturing a semiconductor device according to claim 1, wherein, after the step (f), the method further comprises:

(g) stacking a silicide layer of a first refractory metal, a nitride layer of the first refractory metal, and a second refractory metal layer in sequence on the amorphousized surface layer to form stacked layers,

(h) forming a hard mask made of an insulating film on the stacked layers after the step (g), and

(i) etching the stacked layers and the polysilicon layer by using the hard mask as a mask; and

wherein a poly-metal gate electrode including the polysilicon layer having the first conductivity type is formed in the forming region of the grooved gate transistor and a poly-metal gate electrode including the polysilicon layer having the second conductivity type is formed in the forming region of the planar gate transistor.

6. The method for manufacturing a semiconductor device according to claim 5, wherein

the first conductivity type is N-type, and

the second conductivity type is P-type.

7. The method for manufacturing a semiconductor device according to claim 6, wherein

the impurity of the first conductivity type is phosphorous, and

the impurity of the second conductivity type is boron.

8. The method for manufacturing a semiconductor device according to claim 5, wherein

the silicide layer of the first refractory metal is a tungsten silicide (WSi₂) layer,

the nitride layer of the first refractory metal is a tungsten nitride (WN) layer, and

the second refractory metal layer is a tungsten layer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein

the tungsten silicide layer is formed by a CVD method using dichlorosilane (SiH₂Cl₂) and tungsten hexafluoride (WF₆) and a material gas.

10. The method for manufacturing a semiconductor device according to claim 9, wherein

the tungsten silicide layer is formed into a continuous layer in the N-type region and into a discontinuous layer in the P-type region, respectively.

11. The method for manufacturing a semiconductor device according to claim 10, wherein

the step of forming the tungsten silicide layer further comprises after forming the tungsten silicide layer:

(j) forming a silicon layer on the tungsten silicide layer, and

(k) heat treating the semiconductor substrate forming the tungsten silicide layer, and

wherein due to heat in the step (k), the amorphousized surface layer is turned into a polysilicon layer and simultaneously impurities in the polysilicon layer are activated.