Data transfer control device and electronic instrument

• US 20080215789A1
• Filed: 02/04/2008
• Published: 09/04/2008
• Est. Priority Date: 02/19/2007
• Status: Abandoned Application

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Saito, Nobuyuki, Nishida, Haruo, Matsuda, Kuniaki, Akiyama, Chisato
• Application Number:
  US12/068,180
• Publication Number:
  US 20080215789A1
• Time in Patent Office: Days
• US Class Current: 710/308
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A data transfer control device includes a PATA I/F connected to a PATA bus, a SATA I/F connected to a SATA bus, and a sequence controller that controls a transfer sequence. The PATA I/F includes a task file register that is a pseudo register provided to implement a PATA/SATA bus bridge, and the SATA I/F includes a shadow task file register, a register value being transferred between the shadow task file register and the task file register.

Claims

1. A data transfer control device that has a Parallel ATA/Serial ATA bus bridge function, the data transfer control device comprising:

a Parallel ATA interface that is connected to a Parallel ATA bus and provides an interface with a host;

a Serial ATA interface that is connected to a Serial ATA bus and provides an interface with a Serial ATA device; and

a sequence controller that controls a transfer sequence,

the Parallel ATA interface including a task file register that is a pseudo register provided to implement a Parallel ATA/Serial ATA bus bridge; and

the Serial ATA interface including a shadow task file register, a register value being transferred between the task file register and the shadow task file register.

2. The data transfer control device as defined in claim 1, the data transfer control device further comprising:

a data buffer that buffers data transferred between the host and the Serial ATA device,

data being transferred between the host and the Serial ATA device through the data buffer; and

the register value being transferred between the task file register and the shadow task file register through the sequence controller.

3. The data transfer control device as defined in claim 2, the sequence controller outputting a transfer start signal, a transfer stop signal, and a transfer direction setting signal to the Parallel ATA interface and the Serial ATA interface to control a transfer sequence of data transferred between the host and the Serial ATA device through the data buffer.

4. The data transfer control device as defined in claim 1, when the host reads data from the Serial ATA device, the sequence controller setting the register value in the task file register after data transfer from the Parallel ATA interface to the host has been completed.

5. The data transfer control device as defined in claim 1, when the host writes data into the Serial ATA device, the sequence controller setting the register value in the task file register after the sequence controller has received an FIS from the Serial ATA device, the FIS indicating completion of data transfer through the Serial ATA bus.

6. The data transfer control device as defined in claim 1, the sequence controller transferring the register value from the task file register to the shadow task file register on condition that a parameter has been written into the task file register and then an ATA command has been written into the task file register.

7. The data transfer control device as defined in claim 6,

the Parallel ATA interface activating a command write detection signal when the ATA command has been written into the task file register;

and

the sequence controller transferring the register value from the task file register to the shadow task file register when the command write detection signal has been activated.

8. The data transfer control device as defined in claim 1,

each bit of a register group of the task file register and corresponding bit of a register group of the shadow task file register being connected through the sequence controller;

and

the sequence controller generating a transfer trigger signal of the register value, and transferring the register value between the task file register and the shadow task file register based on the generated transfer trigger signal.

9. The data transfer control device as defined in claim 1,

the Serial ATA interface decoding an FIS received from the Serial ATA device, and generating and outputting an interrupt signal that notifies the sequence controller of the type of the FIS based on the decoding result;

and

the sequence controller determining the type of the FIS based on the interrupt signal from the Serial ATA interface, and controlling a transfer sequence of data and the register value.

10. The data transfer control device as defined in claim 1,

when a soft reset bit of the task file register has been set at 1, the sequence controller transferring the register value from the task file register to the shadow task file register, the soft reset bit of the register value being set at 1;

the Serial ATA interface transmitting a register FIS to the Serial ATA device, the soft reset bit of the register FIS being set at 1;

when the soft reset bit has been cleared to 0, the sequence controller transferring the register value from the task file register to the shadow task file register, the soft reset bit of the register value being cleared to 0, and starting a soft reset initialization sequence process of the data transfer control device; and

the Serial ATA interface causing the Serial ATA device to perform a soft reset initialization sequence process by transmitting a register FIS to the Serial ATA device, the soft reset bit of the register FIS being cleared to 0.

11. The data transfer control device as defined in claim 10,

the Parallel ATA interface outputting a soft reset detection signal to the sequence controller;

and

the sequence controller transferring the register value based on the soft reset detection signal output from the Parallel ATA interface.

12. An electronic instrument comprising:

the data transfer control device as defined in claim 1;

a host that is connected to the data transfer control device; and

a Serial ATA device that is connected to the data transfer control device.

13. An electronic instrument comprising:

the data transfer control device as defined in claim 2;

a host that is connected to the data transfer control device; and

a Serial ATA device that is connected to the data transfer control device.

14. An electronic instrument comprising:

the data transfer control device as defined in claim 6;

a host that is connected to the data transfer control device; and

a Serial ATA device that is connected to the data transfer control device.

15. An electronic instrument comprising:

the data transfer control device as defined in claim 10;

a host that is connected to the data transfer control device; and

a Serial ATA device that is connected to the data transfer control device.