Hybrid SSD Using A Combination of SLC and MLC Flash Memory Arrays

• US 20080215800A1
• Filed: 10/29/2007
• Published: 09/04/2008
• Est. Priority Date: 01/06/2000
• Status: Active Grant

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Shen, Ming-Shiang, Lee, Charles C., Chow, David Q., Ma, Abraham Chih-Kang, Yu, I-Kang
• Granted Patent: US 8,078,794 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/1416 by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights G06F12/1458 takes precedence
• CPC Class Codes: G06F 21/32 using biometric data, e.g. fingerprints, iris scans or voiceprints
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0643 Management of files
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G07C 9/257 electronically G07C9/26 takes precedence
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Hybrid solid state drives (SSD) using a combination of single-level cell (SLC) and multi-level cell (MLC) flash memory arrays are described. According to one aspect of the present invention, a hybrid SSD is built using a combination SLC and MLC flash memory arrays. The SSD also includes a micro-controller to control and coordinate data transfer from a host computing device to either the SLC flash memory array of the MLC flash memory array. A memory selection indicator is determined by triaging data file based on one or more criteria, which include, but is not limited to, storing system files and user directories in the SLC flash memory array and storing user files in the MLC flash memory array; or storing more frequent access files in the SLC flash memory array, while less frequent accessed files in the MLC flash memory array.

Claims

1. A hybrid solid state drive (SSD) apparatus comprising:

an interface configured for receiving data transfer commands from a host computing device, each of the received data transfer commands includes either a data read or a data write request;

a single-level cell (SLC) flash memory array;

a multi-level cell (MLC) flash memory array;

a micro-controller configured for controlling the interface, the SLC flash memory array and MLC flash memory array, the micro-processor extracts particular characteristics of a data file associated with said each of the received data transfer commands, and then, based on the particular characteristics for the data write request, a memory selection indicator is determined by triaging the data file to be stored in either the SLC flash memory array or the MLC flash memory array based on one or more criteria; and

an address mapping memory, coupling to the micro-controller, configured to correlate logical block address (LBA) of the data file to a physical block address (PBA) associated with one of the SLC flash memory array and the MLC flash memory array according to the memory selection indicator.

2. The apparatus of claim 1 further comprises:

a read cache configured to be a first buffer holding data blocks to be transferred to the host computing device; and

a write cache configured to be a second buffer holding data blocks to be written to either the SLC or MLC flash memory array.

3. The apparatus of claim 2 further comprises one or more register files configured to hold the particular characteristics for the micro-controller.

4. The apparatus of claim 3 further comprises a memory switch configured to switch between the SLC flash memory array and the MLC flash memory array based on the memory selection indicator.

5. The apparatus of claim 1, wherein the memory selection indicator is associated with the LBA in the address mapping memory

6. The apparatus of claim 1, wherein one of the one or more criteria comprises the SLC flash memory array is configured to store system files and user directories and the MLC memory array is configured to store user files.

7. The apparatus of claim 1, wherein one of the one or more criteria comprises the SLC flash memory array is configured to store more frequent accessed files and the MLC flash memory array is configured to store less frequent accessed files.

8. The apparatus of claim 7, wherein the more frequent accessed files are on-going project data files and the less frequent accessed files are archival data files.

9. The apparatus of claim 1, wherein the particular characteristics of the data file includes, but is not limited to, the data file'"'"'s name, the data file'"'"'s type, the data file'"'"'s access frequency, the data file'"'"'s size, said LBA of the data file.

10. A method of writing data in a hybrid solid state drive (SSD) comprising:

receiving data transfer commands;

determining whether each of the received data transfer commands is a data read or a data write request;

when the data write request is determined,

extracting particular characteristics of a data file associated with said each of the received data transfer commands;

constructing a memory selection indicator by triaging the data file to be stored in either a SLC flash memory array or a MLC flash memory array using the particular characteristics based on one or more criteria;

correlating logical block address (LBA) of the data file to a physical block address (PBA) associated with one of the SLC flash memory array and the MLC flash memory array according to the memory selection indicator; and

writing data blocks to the physical block address accordingly.

11. The method of claim 10 further comprises pre-storing the data blocks associated with LBA to a write cache when the data write request is determined.

12. The method of claim 11 further comprises storing the particular characteristics of the data file into one or more register files of the micro-controller.

13. The method of claim 10, wherein one of the one or more criteria comprises the SLC flash memory array is configured to store system files and user directories and the MLC memory array is configured to store user files.

14. The method of claim 13, wherein each of the user directories is determined by examining whether there are double linking pointers associated therewith.

15. The method of claim 14, wherein the double linking pointers consist of a “

dot” and

a “

dotdot”

in first and second records of said each of the user directories, respectively.

16. The method of claim 10, wherein one of the one or more criteria comprises the SLC flash memory array is configured to store more frequent accessed files and the MLC flash memory array is configured to store less frequent accessed files.

17. The method of claim 16, wherein the more frequent accessed files are on-going project data files and the less frequent accessed files are archival data files.

18. The method of claim 10, wherein one of the one or more criteria comprises the SLC flash memory array is configured to store a set of data files having a prefix “

SLC”

.

19. The method of claim 10, wherein one of the one or more criteria comprises the MLC memory array is configured to store a set of data files having a prefix “

MLC”

.

20. The method of claim 10, wherein the particular characteristics of the data file includes, but is not limited to, the data file'"'"'s name, the data file'"'"'s type, the data file'"'"'s access frequency, the data file'"'"'s size, said LBA of the data file.