Portable Data Storage Using Slc and Mlc Flash Memory

• US 20080215801A1
• Filed: 09/29/2005
• Published: 09/04/2008
• Est. Priority Date: 09/29/2005
• Status: Active Grant

• Current Assignee: Trek 2000 International Limited (Trek Technology Singapore PTE Limited)
• Original Assignee: Trek 2000 International Limited (Trek Technology Singapore PTE Limited)
• Inventors: Tan, Henry, Poo, Teng Pin, Ooi, Chin Shyan Raymond
• Granted Patent: US 8,521,945 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A portable data storage device is disclosed that includes an interface (3) for enabling the portable data storage device to be used for data transfer with a host computer (5), and an interface controller (2) for controlling the interface (3). There is also a master controller (7) for controlling the writing of data to and reading of data from a non-volatile memory (8, 9). The non-volatile memory is at least one single level cell (SLC) flash memory (8) and at least one multiple level cell (MLC) flash memory (9). The at least one single level cell flash memory (8) and at least one multiple level cell flash memory (9) are able to operate simultaneously for improving the speed of operation over onl multiple level cell flash memory.

Claims

1. A portable data storage device comprising:

(a) an interface for enabling the portable data storage device to be used for data transfer with a host computer;

(b) an interface controller for controlling the interface;

(c) a master controller for controlling the writing of data to and reading data from a non-volatile memory;

(d) the non-volatile memory comprising at least one single layer cell flash memory and at least one multiple layer cell flash memory;

(e) the at least one single layer cell flash memory and at least one multiple layer cell flash memory being able to operate simultaneously for improving the speed of operation over only multiple layer flash memory.

2. A portable data storage device as claimed in claim 1 further comprising at least one data bus operatively connected to the master controller and the at least one single layer cell flash memory and at least one multiple layer cell flash memory for writing data to and reading data from the at least one single layer cell flash memory and at least one multiple layer cell flash memory.

3. A portable data storage device as claimed in claim 2, wherein the at least one data bus comprises a common data bus for both the at least one single layer cell flash memory and at least one multiple layer cell flash memory.

4. A portable data storage device as claimed in claim 2, wherein the at least one data bus comprises a first data bus operatively connected to the at least one single layer cell flash memory and a second bus operatively connected to the at least one multiple layer cell flash memory.

5. A portable data storage device as claimed in claim 3, wherein the master controller is for writing data to and reading data from the at least one single layer cell flash memory and the at least one multiple layer cell flash memory alternately;

data being written to and read from the at least one single layer cell flash memory at a speed a multiplication factor higher than those of the at least one multiple layer cell flash memory;

the data being in the form selected from the group consisting of;

blocks, and page.

6. A portable data storage device as claimed in claim 5, wherein the multiplication factor is in the range 5 to 10.

7. A portable data storage device as claimed in claim 5, wherein each block of data for the at least one single layer cell flash memory is 64 pages;

and each block of data for the at least one multiple layer cell flash memory is 128 pages.

8. A portable data storage device as claimed in claim 4, wherein the master controller is for writing data to and reading data from the at least one single layer cell flash memory and the at least one multiple layer cell flash memory simultaneously, the data being in a form selected from the group consisting of:

blocks, and page.

9. A portable data storage device as claimed in claim 8, wherein the data being written to and read from the at least one single layer cell flash memory is at a speed a multiplication factor higher than that of the at least one multiple layer cell flash memory.

10. A portable data storage device as claimed in claim 9, wherein the multiplication factor is in the range 5 to 10.

11. A portable data storage device as claimed in claim 8, wherein each block of data for the at least one single layer cell flash memory is 64 pages;

and each block of data for the at least one multiple layer cell flash memory is 128 pages;

each page being 2048 bytes.

12. A portable data storage device as claimed in claim 4, where the first data bus is one of:

an upper data bus and a lower data bus, and the second data bus is the other of the upper data bus and the lower data bus.

13. A method of processing data on a portable data storage device, the portable data storage device comprising a master controller for controlling a memory, the memory comprising at least one single layer cell flash memory and at least one multiple layer cell flash memory, the method comprising:

using the master controller to control the writing of data to and reading data from a non-volatile memory such that the at least one single layer cell flash memory and at least one multiple layer cell flash memory have data written to and read from them simultaneously.

14. A method as claimed in claim 13 further comprising writing data to and reading data from the at least one single layer cell flash memory and at least one multiple layer cell flash memory over at least one data bus operatively connected to the master controller and the at least one single layer cell flash memory and at least one multiple layer cell flash memory.

15. A method as claimed in claim 14, wherein the at least one data bus comprises a common data bus for both the at least one single layer cell flash memory and at least one multiple layer cell flash memory.

16. A method as claimed in claim 14, wherein the at least one data bus comprises a first data bus operatively connected to the at least one single layer cell flash memory and a second data bus operatively connected to the at least one multiple layer cell flash memory.

17. A method as claimed in claim 16, wherein the first data bus is one of:

an upper data bus and a lower data bus, and the second data bus is the other of the upper data bus and the lower data bus.

18. A method as claimed in claim 15, wherein the master controller writes data to and reads data from the at least one single layer cell flash memory the and at least one multiple layer cell flash memory alternately;

data being written to and read from the at least one single layer cell flash memory at a speed a multiplication factor higher than those of the at least one multiple layer cell flash memory;

the data being in a form selected from the group consisting of;

blocks, and page.

19. A method as claimed in claim 18, wherein the multiplication factor is in the range 5 to 10.

20. A method as claimed in claim 19, wherein each block of data for the at least one single layer cell flash memory is 64 pages;

and each block of data for the at least one multiple layer cell flash memory is 128 pages.

21. A method as claimed in claim 16, wherein the master controller writes data to and reads data from the at least one single layer cell flash memory and the at least one multiple layer cell flash memory simultaneously, the data being in a form selected from the group consisting of:

blocks, and page.

22. A method as claimed in claim 21, wherein the data is written to and read from the at least one single layer cell flash memory at a speed a multiplication factor higher than that of the at least one multiple layer cell flash memory.

23. A method as claimed in claim 22, wherein the multiplication factor is in the range 5 to 10.

24. A method as claimed in claim 21, wherein each block of data for the at least one single layer cell flash memory is 64 pages;

and each block of data for the at least one multiple layer cell flash memory is 128 pages;

each page being 2048 bytes