SYSTEM AND METHOD OF IMPROVING TASK SWITCHING AND PAGE TRANSLATION PERFORMANCE UTILIZING A MULTILEVEL TRANSLATION LOOKASIDE BUFFER

• US 20080215815A1
• Filed: 04/11/2008
• Published: 09/04/2008
• Est. Priority Date: 03/31/2005
• Status: Active Grant

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Kornegay, Marcus Lathan, Pase, Douglas Michael, DOMBROWSKI, CHRIS
• Granted Patent: US 7,783,835 B2
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/654 Look-ahead translation
• CPC Class Codes: G06F 2212/681 Multi-level TLB, e.g. microTLB and main TLB

Abstract

A system and method of improved task switching in a data processing system. First, a first-level cache memory casts out an invalidated page table entry and an associated first page directory base address to a second-level cache memory. Then, the second-level cache memory determines if a task switch has occurred. If a task switch has not occurred, first-level cache memory sends the invalidated page table entry to a current running task directory. If a task switch has occurred, first-level cache memory loads from the second-level cache directory a collection of page table entries related to a new task to enable improved task switching without requiring access to a page table stored in main memory to retrieve the collection of page table entries.

Claims

1. A data processing system, comprising:

a system memory, including a page table; and

a processor, coupled to said system memory via an interconnect, wherein said processor further includes;

a translation lookaside buffer (TLB) that determines whether a task switch has occurred, wherein the TLB includes;

a first-level cache memory that casts out an invalidated page table entry and associated first page directory base address; and

a second-level cache memory coupled to said first-level cache memory, wherein said second-level cache memory includes a second-level cache directory including;

a current-running task directory associated with a first task for storing at least one page table entry evicted from said first-level cache memory;

a task switch directory for storing at least one plurality of page table entries associated with at least one other task and sending a first plurality of page table entries associated with a new task to enable improved task switching without requiring access to said page table stored in said system memory to retrieve said first plurality of page table entries.

2. The data processing system according to claim 1, wherein said second-level cache directory sends at least one speculative load request to said system memory for a second plurality of page table entries related to said new task, in response to determining said task switch has occurred.

3. The data processing system according to claim 2, wherein said second-level cache directory parses said task switch directory for a second page directory base address associated with said new task, in response to determining said task switch has occurred and loads said second plurality of page table entries related to said new task, in response to determining said task switch does not include said second page directory base address.

4. The data processing system according to claim 1, wherein said processor starts executing said new task, in response to loading said first plurality of page table entries.

5. The data processing system according to claim 1, wherein said second-level cache directory determines whether said task switch directory is full and in response to determining said task switch directory is full, casts out a page directory base address and a plurality of associated page table entries from said task switch directory, and merges into a list a plurality of page table entries from said first-level cache memory with a plurality of page table entries stored in said current-running task directory, and stores said list in said task switch directory.

6. The data processing system according to claim 1, wherein said second-level cache directory determines whether a requested page table entry is stored in said current-running task directory, in response to determining said task switch has not occurred.

7. The data processing system according to claim 1 wherein said second-level cache directory sends a speculative load request for a requested page table entry, in response to determining said task switch has not occurred.

8. The data processing system according to claim 1, wherein said second-level cache directory evicts a page table entry from said current-running task directory, in response to determining said task switch has not occurred, and adds said invalidated page table entry to said current-running task directory, in response to evicting said page table entry from said current running task directory.

9. A processor, comprising:

a translation lookaside buffer (TLB) that determines whether a task switch has occurred, wherein the TLB includes;

a first-level cache memory that casts out an invalidated page table entry and associated first page directory base address; and

a second-level cache memory coupled to said first-level cache memory, wherein said second-level cache memory includes a second-level cache directory including;

a current-running task directory associated with a first task for storing at least one page table entry evicted from said first-level cache memory;

a task switch directory for storing at least one plurality of page table entries associated with at least one other task and sending a first plurality of page table entries associated with a new task to enable improved task switching without requiring access to said page table stored in a system memory to retrieve said first plurality of page table entries.

10. The processor of claim 9, wherein said second-level cache directory sends at least one speculative load request to said system memory for a second plurality of page table entries related to said new task, in response to determining said task switch has occurred.

11. The processor of claim 10, wherein said second-level cache directory parses said task switch directory for a second page directory base address associated with said new task, in response to determining said task switch has occurred and loads said second plurality of page table entries related to said new task, in response to determining said task switch does not include said second page directory base address.

12. The processor of claim 9, wherein said processor starts executing said new task, in response to loading said first plurality of page table entries.

13. The processor of claim 9, wherein said second-level cache directory determines whether said task switch directory is full and in response to determining said task switch directory is full, casts out a page directory base address and a plurality of associated page table entries from said task switch directory, and merges into a list a plurality of page table entries from said first-level cache memory with a plurality of page table entries stored in said current running task directory, and stores said list in said task switch directory.

14. The processor of claim 9, wherein said second-level cache directory determines whether a requested page table entry is stored in said current-running task directory, in response to determining said task switch has not occurred.

15. The processor of claim 9, wherein said second-level cache directory sends a speculative load request for a requested page table entry, in response to determining said task switch has not occurred.

16. The processor of claim 9, wherein said second-level cache directory evicts a page table entry from said current-running task directory, in response to determining said task switch has not occurred, and adds said invalidated page table entry to said current-running task directory, in response to evicting said page table entry from said current-running task directory.

17. A computer program product for improved task switching in a data processing system, comprising:

instructions, stored on computer-readable storage media, for casting out an invalidated page table entry and associated first page directory base address from a first-level cache memory to a second-level cache memory;

instructions, stored on computer-readable storage media, in response to said casting out, for determining whether a task switch has occurred;

instructions, stored on computer-readable storage media, in response to determining a task switch has not occurred, for sending said invalidated page table entry to a current running task directory; and

instructions, stored on computer-readable storage media, in response to determining said task switch has occurred, for loading from a task switch directory a first plurality of page table entries related to a new task to enable improved task switching without requiring access to a page table stored in main memory to retrieve said first plurality of page table entries.

18. The computer program product according to claim 17, further including:

instructions, stored on computer-readable storage media, in response to determining said task switch has occurred, for sending at least one speculative load request to a system memory for a second plurality of page table entries related to said new task.

19. The computer program product according to claim 18, further including:

instructions, stored on computer-readable storage media, in response to determining said task switch has occurred, for parsing said task switch directory for a second page directory base address associated with said new task; and

instructions, stored on computer-readable storage media, in response to determining said task switch directory does not include said second page directory base address, for loading said second plurality of page table entries related to said new task.

20. The computer program product according to claim 18, further including:

instructions, stored on computer-readable storage media, in response to said loading, for starting execution of said new task.

21. The computer program product according to claim 17, further including:

instructions, stored on computer-readable storage media, for determining whether said task switch directory is full;

instructions, stored on computer-readable storage media, in response to determining said task switch directory is full, for casting out a page directory base address and a plurality of associated page table entries from said task switch directory; and

instructions, stored on computer-readable storage media, for merging into a list a plurality of page table entries from said first-level cache memory with a plurality of page table entries stored in said current-running task directory; and

instructions, stored on computer-readable storage media, for storing said list in said task switch directory.

22. The computer program product according to claim 17, further including:

instructions, stored on computer-readable storage media, in response to determining said task switch has not occurred, for determining whether a requested page table entry is stored in said current-running task directory.

23. The computer program product according to claim 17, further including:

instructions, stored on computer-readable storage media, in response to determining said task switch has not occurred, for sending a speculative load request for a requested page table entry.

24. The computer program product according to claim 17, further including:

instructions, stored on computer-readable storage media, in response to determining said task switch has not occurred, for evicting a page table entry from said current-running task directory; and

instructions, stored on computer-readable storage media, in response to said evicting, for adding said invalidated page table entry to said current-running task directory.