SYSTEM AND METHOD OF IMPROVING TASK SWITCHING AND PAGE TRANSLATION PERFORMANCE UTILIZING A MULTILEVEL TRANSLATION LOOKASIDE BUFFER
First Claim
1. A data processing system, comprising:
- a system memory, including a page table; and
a processor, coupled to said system memory via an interconnect, wherein said processor further includes;
a translation lookaside buffer (TLB) that determines whether a task switch has occurred, wherein the TLB includes;
a first-level cache memory that casts out an invalidated page table entry and associated first page directory base address; and
a second-level cache memory coupled to said first-level cache memory, wherein said second-level cache memory includes a second-level cache directory including;
a current-running task directory associated with a first task for storing at least one page table entry evicted from said first-level cache memory;
a task switch directory for storing at least one plurality of page table entries associated with at least one other task and sending a first plurality of page table entries associated with a new task to enable improved task switching without requiring access to said page table stored in said system memory to retrieve said first plurality of page table entries.
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Accused Products
Abstract
A system and method of improved task switching in a data processing system. First, a first-level cache memory casts out an invalidated page table entry and an associated first page directory base address to a second-level cache memory. Then, the second-level cache memory determines if a task switch has occurred. If a task switch has not occurred, first-level cache memory sends the invalidated page table entry to a current running task directory. If a task switch has occurred, first-level cache memory loads from the second-level cache directory a collection of page table entries related to a new task to enable improved task switching without requiring access to a page table stored in main memory to retrieve the collection of page table entries.
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Citations
24 Claims
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1. A data processing system, comprising:
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a system memory, including a page table; and a processor, coupled to said system memory via an interconnect, wherein said processor further includes; a translation lookaside buffer (TLB) that determines whether a task switch has occurred, wherein the TLB includes; a first-level cache memory that casts out an invalidated page table entry and associated first page directory base address; and a second-level cache memory coupled to said first-level cache memory, wherein said second-level cache memory includes a second-level cache directory including; a current-running task directory associated with a first task for storing at least one page table entry evicted from said first-level cache memory; a task switch directory for storing at least one plurality of page table entries associated with at least one other task and sending a first plurality of page table entries associated with a new task to enable improved task switching without requiring access to said page table stored in said system memory to retrieve said first plurality of page table entries. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A processor, comprising:
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a translation lookaside buffer (TLB) that determines whether a task switch has occurred, wherein the TLB includes; a first-level cache memory that casts out an invalidated page table entry and associated first page directory base address; and a second-level cache memory coupled to said first-level cache memory, wherein said second-level cache memory includes a second-level cache directory including; a current-running task directory associated with a first task for storing at least one page table entry evicted from said first-level cache memory; a task switch directory for storing at least one plurality of page table entries associated with at least one other task and sending a first plurality of page table entries associated with a new task to enable improved task switching without requiring access to said page table stored in a system memory to retrieve said first plurality of page table entries. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A computer program product for improved task switching in a data processing system, comprising:
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instructions, stored on computer-readable storage media, for casting out an invalidated page table entry and associated first page directory base address from a first-level cache memory to a second-level cache memory; instructions, stored on computer-readable storage media, in response to said casting out, for determining whether a task switch has occurred; instructions, stored on computer-readable storage media, in response to determining a task switch has not occurred, for sending said invalidated page table entry to a current running task directory; and instructions, stored on computer-readable storage media, in response to determining said task switch has occurred, for loading from a task switch directory a first plurality of page table entries related to a new task to enable improved task switching without requiring access to a page table stored in main memory to retrieve said first plurality of page table entries. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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Specification