REMOTE BIST FOR HIGH SPEED TEST AND REDUNDANCY CALCULATION
First Claim
1. A method of testing embedded memory arrays in functional circuitry within an integrated circuit using a built-in self test (BIST) architecture, said method comprising:
- performing, by a BIST logic controller, test functions common to all of said embedded memory arrays said BIST logic controller being remote from said embedded memory arrays and operating at a lower frequency than said embedded memory arrays;
sending, by said BIST logic controller, instructions to a plurality of blocks of test logic,each one of said blocks being incorporated into a corresponding one of said embedded memory arrays and operating at a same frequency as said corresponding one of said embedded memory array, said same frequency comprising a higher frequency relative to said lower frequency of said BIST logic controller; and
performing, by said each one of said blocks, test functions unique to said corresponding one of said embedded memory arrays, said performing comprising;
increasing the frequency of said instructions to said higher frequency.
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Accused Products
Abstract
Disclosed in a hybrid built-in self test (BIST) architecture for embedded memory arrays that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A standalone BIST logic controller operates at a lower frequency and communicates with a plurality of embedded memory arrays using a BIST instruction set. A block of higher-speed test logic is incorporated into each embedded memory array under test and locally processes BIST instructions received from the standalone BIST logic controller at a higher frequency. The higher-speed test logic includes a multiplier for increasing the frequency of the BIST instructions from the lower frequency to the higher frequency. The standalone BIST logic controller enables a plurality of higher-speed test logic structures in a plurality of embedded memory arrays.
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Citations
13 Claims
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1. A method of testing embedded memory arrays in functional circuitry within an integrated circuit using a built-in self test (BIST) architecture, said method comprising:
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performing, by a BIST logic controller, test functions common to all of said embedded memory arrays said BIST logic controller being remote from said embedded memory arrays and operating at a lower frequency than said embedded memory arrays; sending, by said BIST logic controller, instructions to a plurality of blocks of test logic, each one of said blocks being incorporated into a corresponding one of said embedded memory arrays and operating at a same frequency as said corresponding one of said embedded memory array, said same frequency comprising a higher frequency relative to said lower frequency of said BIST logic controller; and performing, by said each one of said blocks, test functions unique to said corresponding one of said embedded memory arrays, said performing comprising; increasing the frequency of said instructions to said higher frequency. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of testing embedded memory arrays in functional circuitry within an integrated circuit using a built-in self test (BIST) architecture, said method comprising:
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performing, by a BIST logic controller, test functions common to all of said embedded memory arrays, said BIST logic controller being separate from said embedded memory arrays and operating at a lower frequency than said embedded memory arrays; sending, by said BIST logic controller, instructions a plurality of blocks of test logic, said sending comprising using a bus connecting said BIST logic controller to said blocks of test logic so as to allow communication from said BIST logic controller to said blocks, said bus operating at said lower frequency of said BIST logic controller, each one of said blocks being incorporated into a corresponding one of said embedded memory arrays and operating at a same frequency as said corresponding one of said embedded memory arrays, said same frequency comprising a higher frequency relative to said lower frequency of said BIST logic controller and said bus; and performing, by each of said blocks, test functions unique to said corresponding one of said embedded memory arrays, said performing comprising; increasing the frequency of said instructions to said higher frequency. - View Dependent Claims (9, 10, 11, 12, 13)
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Specification