Timing Driven Force Directed Placement Flow

• US 20080216038A1
• Filed: 12/29/2007
• Published: 09/04/2008
• Est. Priority Date: 06/29/2005
• Status: Active Grant

• Current Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Original Assignee: Otrsotech LLC (Intellectual Ventures LLC)
• Inventors: Bose, Subhasis
• Granted Patent: US 7,752,588 B2
• Time in Patent Office: Days
• US Class Current: 716/8
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

Techniques for placement of integrated circuit elements include global placement, detailed placement, timing closure, and routing. The integrated circuit is described by a netlist specifying interconnections of morphable devices. The detailed placement uses, for example, Simultaneous Dynamical Integration, wherein the morphable-devices correspond to nodes influenced by forces, including timing forces. The timing forces are derived, for example, from a timing graph; path delay; slack; and drive resistance of the elements. The timing closure uses timing-driven buffering and timing-driven resizing to reduce maximum delay and/or transition time, and/or to fix hold time. Nets having high capacitance and/or fanout, and timing critical nets are preferentially processed. Timing-driven buffering applies buffering solutions to segments of route trees, combines solutions of adjoining segments, and prunes sets of solutions. Timing-driven resizing morphably replaces selected elements with upsized versions thereof.

Claims

1. A method comprising:

determining a particular net requiring buffering from among a plurality of nets of a circuit description;

decomposing a resource into a set of primitives of a structured array architecture; and

allocating at least some of the set of primitives to the particular net.