Apparatus for executing programs for a first computer architechture on a computer of a second architechture

• US 20080216073A1
• Filed: 09/25/2007
• Published: 09/04/2008
• Est. Priority Date: 01/28/1999
• Status: Active Grant

• Current Assignee: Advanced Silicon Technologies LLC
• Original Assignee: ATI International SRL (Advanced Micro Devices, Inc.)
• Inventors: Nijhawan, Sandeep, Van Dyke, Korbin S., Storch, Matthew F., Jurich, Dale R., Yates, John S.
• Granted Patent: US 8,127,121 B2
• Time in Patent Office: Days
• US Class Current: 718/100
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/45554 Instruction set architectures of guest OS and hypervisor or native processor differ, e.g. Bochs or VirtualPC on PowerPC MacOS

Abstract

Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread'"'"'s context. Without modifying a pre-existing operating system of the computer, an entry exception is establishing to be raised on each entry to the operating system at a specified entry point or on a specified condition. The entry exception has an associated entry handler programmed to save a context of an interrupted thread and modify the thread context before delivering the modified context to the operating system. A resumption exception is established to be raised on each resumption from the operating system complementary to one of the specified entries. The resumption exception has an associated exit handler programmed to restore the context saved by a corresponding execution of the entry handler. The entry exception, exit exception, entry handler, and exit handler are cooperatively designed to maintain an association between a one of the threads and an extended context of the thread through a context change induced by the operating system, the extended context including resources of the computer associated with the thread beyond those resources whose association with the thread is maintained by the operating system.

Claims

1. A computer, comprising:

an entry exception raised on entry to a pre-existing operating system at a specified entry point or on a specified condition without modifying said pre-existing operating system of the computer, the entry exception having an associated entry handler, the entry handler programmed to save a context of an interrupted thread and modify the thread context before delivering the modified thread context to the operating system;

a resumption exception raised on resumption from the operating system when such resumption is complementary to one of the specified entries without modifying the operating system, the resumption exception having an associated exit handler, the exit handler programmed to restore the context saved by a corresponding execution of the entry handler;

concurrent threads of control scheduled by the operating system, each thread having an associated context, the association between a thread and a set of computer resources of the associated context maintained by the operating system;

a detector for detecting a specified entry to the operating system from an interrupted thread of the computer, an operator responsive to said detector for raising and servicing the entry exception; and

a further detector for detecting a complementary resumption, a further operator responsive to said further detector for raising and servicing the resumption exception, and returning control to the interrupted thread;

the entry exception, resumption exception, entry handler, and exit handler cooperatively designed to maintain an association between one of the threads and an extended context of the thread through a context change induced by the operating system, the extended context including resources of the computer associated with the thread that are beyond those resources whose association with the thread is maintained by the operating system.

2. The computer of claim 1, wherein the operating system is an operating system for a computer architecture other than the architecture native to the computer.

3. The computer of claim 1, wherein the operating-system-maintained resources of the thread context include data registers of the non-native computer architecture, the computer further comprising:

modifier modifying at least half of the data registers of the portion of the thread context maintained by the operating system before delivering the thread to the non-native operating system.

4. The computer of claim 1, wherein the thread scheduler and the thread execute in different instruction sets of the computer, and the entry and exit exceptions are automatic, without explicit software request, on a transition between the thread instruction set and the operating system instruction set.

5. A computer, comprising:

thread scheduler of said computer scheduling concurrent threads of control, each thread having an associated context, an association between a thread and a set of computer resources of the associated context maintained by the thread scheduler; and

an association between one of the threads and an extended context of the thread through a context change induced by the thread scheduler, which is maintained without modifying the thread scheduler, the extended context including resources of the computer associated with the thread that are beyond those resources whose association with the thread is maintained by the thread scheduler.

6. The computer of claim 5, wherein the thread scheduler is a component of an operating system of the computer, and said computer further comprising:

an entry exception raised on entry to the operating system at a specified entry point or on a specified condition;

a resumption exception raised on a resumption from the operating system following on a specified entry;

a detector for detecting a specified entry to the operating system from an interrupted process of the computer, in response to said detector an operator raising the entry exception, and establishing the association as part of servicing the entry exception; and

another operator raising the resumption exception, and as part of servicing the resumption exception, reestablishing the context in association with the resumed thread returning control to the interrupted process.

7. The computer of claim 6, wherein an exception handler for the entry exception is programmed to save a context of the interrupted process and modify the thread context before delivering the modified thread context to the operating system;

and

an exception handler for the resumption exception is programmed to restore the context saved by a corresponding execution of the entry exception handler.

8. The computer of claim 7, wherein the operating system is an operating system for a computer architecture other than the architecture native to the computer.

9. The computer of claim 8, which additionally executes an operating system native to the computer, and said computer further comprises a classifier that determines the operating system for handling each interrupt or exception.

10. The computer of claim 8, wherein said operating system and the interrupted thread execute in different instruction set architectures of the computer.

11. The computer of claim 6, wherein the operating system is in a binary code for a computer architecture non-native to the architecture of the computer.

12. The computer of claim 11, which additionally executes an operating system native to the computer, and said computer further comprises a classifier that determines the operating system for handling each interrupt or exception.

13. The computer of claim 11, wherein operating system and the interrupted thread execute in different instruction set architectures of the computer.

14. The computer of claim 11, wherein the resources of the context maintained in association with the thread by the non-native operating system include data registers of the non-native computer architecture, the computer further comprising:

a modifier in the entry exception handler, modifying at least half of the data registers of the portion of the process context maintained by the non-native operating system before delivering the process to the non-native operating system, at least some of the modified registers being redundantly written with data to enable checking of the validity of the contents of the context in the resumption exception handler.

15. The computer of claim 6, having different execution modes of the computer for the operating system and the thread, and the association between the thread and the context is automatic, without an explicit software request, on a transition between the thread execution mode and the operating system execution mode.

16. The computer of claim 15, wherein the thread execution mode and the thread scheduler execution mode are two different instruction set architectures of the computer.

17. The computer of claim 6, further comprising:

memory for saving a portion of the context of the computer during servicing the entry exception, and altering the context of an interrupted thread before delivering the interrupted thread and its corresponding context to the operating system.

18. The computer of claim 6, further comprising a linkage return address for resumption of the thread modified to include information used to maintain the association.

19. The computer of claim 18, wherein the modification leaves at least half of the bits of the linkage return address intact.

20. The computer of claim 5, wherein the thread scheduler is an operating system for a computer architecture other than the architecture native to the computer.

21. The computer of claim 20, which additionally executes an operating system native to the computer, and said computer further comprises a classifier that determines the operating system for handling each interrupt or exception.

22. The computer of claim 20, wherein the operating system and the interrupted thread execute in different instruction set architectures of the computer.

23. The computer of claim 5, having different execution modes of the computer for the thread scheduler and the thread, and the association between the thread and the context is automatic, without an explicit software request, on a transition between the thread execution mode and the thread scheduler execution mode.

24. The computer of claim 23, wherein the thread execution mode and the thread scheduler execution mode are two different instruction set architectures of the computer.

25. The computer of claim 23, further comprising a register set to a value that specifies actions to be taken by an exception handler invoked on the transition to convert operands from one form to another to conform to a data storage convention of the thread scheduler execution mode.

26. The computer of claim 5, further comprising:

memory saving a portion of the context of the computer in an interrupt handler of the computer, and a modifier altering the context of an interrupted thread before delivering the interrupted thread and its corresponding context to the thread scheduler.

27. The computer of claim 20, wherein the operating-system-maintained resources of the thread context include data registers of the non-native computer architecture, the computer further comprising:

a modifier for modifying at least half of the data registers of the portion of the thread context maintained by the operating system before delivering the thread to the non-native operating system.

28. The computer of claim 27, wherein at least some of the modified registers are overwritten by a timestamp.

29. The computer of claim 27, wherein at least some of the modified registers are overwritten by information indicating a storage location at which at least the portion of the thread context to be modified is saved before the modifying.

30. The computer of claim 5, further comprising a linkage return address for the thread modified to include information used to maintain the association.

31. The computer of claim 30, wherein the modification leaves at least half of the bits of the linkage return address intact.

32. The computer of claim 5, further comprising either a delay deferring delivery of an interrupt before interrupting the thread by a time sufficient to allow the thread to reach a checkpoint, or a controller rolling execution of the thread back to a checkpoint, where the checkpoints are points in the execution of the thread where the amount of extended context, being the resources of the thread that are beyond those whose resource association with the thread is maintained by the thread scheduler, is reduced.

33. The computer of claim 5, further comprising:

an entry handler for execution at a specified entry point or on a specified entry condition to a preexisting thread scheduler, without modifying said pre-existing thread scheduler, the entry handler programmed to save a context of an interrupted thread and modify the thread context before delivering the modified thread context to the thread scheduler.

34. The computer of claim 20, further comprising:

a service routine of the operating system, a linkage return address passed to the service routine at which to resume execution on completion of the service, the linkage return address deliberately chosen so that an attempt to execute an instruction from the linkage return address on return from the service routine will raise a program execution exception;

a processor attempting to execute the instruction at the linkage return address and raising the chosen exception, on return from the service routine; and

a controller returning control to a caller of the service routine, after servicing the exception.

35. A computer, comprising:

an entry exception raised on entry to a computer operating system at a specified entry point or on a specified condition;

a resumption exception raised on resumption from the operating system when such resumption is complementary to one of the specified entries;

a detector for detecting a specified entry to the operating system from interruption of a process executing on the computer, in response to said detector an operator raising and servicing the entry exception, and then entering the operating system to perform a service associated with the specified operating system entry; and

another detector for detecting a complementary resumption, another operator raising and servicing the resumption exception, and returning control to the interrupted process.

36. The computer of claim 35, wherein an exception handler for the entry exception is programmed to save a context of the interrupted process and to modify the process context before delivering the modified process context to the operating system;

and further comprising;

an exception handler for the resumption exception programmed to restore the context saved by a corresponding execution of the entry exception handler.

37. The computer of claim 36, wherein the operating system is an operating system for a computer architecture other than the architecture native to the computer.

38. The computer of claim 37, wherein the operating system and the interrupted process execute in different instruction set architectures of the computer.

39. The computer of claim 37, wherein the resources of the context maintained in association with the process by the operating system include data registers of the non-native computer architecture, the computer further comprising:

a modifier, in the entry exception handler, for modifying at least half of the data registers of the portion of the process context maintained by the operating system before delivering the process to the non-native operating system, at least some of the modified registers being redundantly written with data to enable checking of the validity of the contents of the context in the resumption exception handler.

40. The computer of claim 36, wherein the operating system and the process execute in two different instruction set architectures of the computer, and the association between the process and the context is automatic, without an explicit software request, on a transition between the instruction set architectures.

41. The computer of claim 36, further comprising a linkage return address for the process modified to include information used to restore the context.

42. The computer of claim 35, wherein the operating system is an operating system for a computer architecture other than the architecture native to the computer, unmodified for execution on the computer.

43. The computer of claim 42, which additionally executes an operating system native to the computer, and said computer further comprises a classifier that determines the operating system for handling each exception.

44. The computer of claim 42, wherein operating system and the interrupted process execute in different instruction set architectures of the computer.

45. The computer of claim 35, wherein the operating system and the interrupted process execute in different execution modes of the computer, and the association between the interrupted process and the context is automatic, without an explicit software request, on a transition between the execution mode of the interrupted process and the execution mode of the operating system.

46. The computer of claim 45, wherein the process execution mode and the operating system execution mode are two different instruction set architectures of the computer.

47. The computer of claim 35, wherein a service routine for the entry exception modifies at least half of the data registers of the portion of a process context maintained in association with the process by the operating system before delivering the process to the non-native operating system.

48. The computer of claim 47, wherein at least some of the modified registers are overwritten by information indicating a storage location at which at least the extended context, the extended context being the resources beyond those whose resource association with the process is maintained by the operating system, is saved before the modifying.

49. The computer of claim 48, wherein at least some of the modified registers are overwritten by a value that enables validation of the contents of the process or extended context.

50. The computer of claim 47, wherein at least some of the modified registers are overwritten by a value that enables validation of the contents of the context.

51. The computer of claim 47, wherein at least some of the modified registers are overwritten by a timestamp.

52. The computer of claim 35, further comprising a linkage return address for the process modified to include information used to maintain the association.

53. The computer of claim 51, wherein the modification leaves at least half of the bits of the linkage return address intact.

54. The computer of claim 35, further comprising:

a linkage return address of the interrupted process which is modified as part of servicing the entry exception, the return address deliberately chosen so that an attempt to execute an instruction from the return address on return from the operating system will raise the resumption exception.

55. The computer of claim 54, wherein the linkage return address points to a memory page having a memory attribute that raises the chosen exception on at attempt to execute an instruction from the page.

56. The computer of claim 35, further comprising either an operator for rolling execution of the process back to a checkpoint in the execution of the process where the amount of extended context, the extended context being the resources of the process context beyond those whose resource association with the process is maintained by the operating system, is reduced.

57. The computer of claim 35, further comprising either a delay deferring delivery of an interrupt before interrupting the process by a time sufficient to allow the process to reach a checkpoint in the execution of the process, where the amount of extended context, the extended context being the resources of the process context beyond those whose resource association with the process is maintained by the operating system, is reduced.

58. A computer comprising:

an operating system;

an interrupted thread;

an entry handler that permits execution at a specified entry point or on a specified entry condition to the operating system, said entry handler obtained without modifying said pre-existing operating system of the computer;

said entry handler programmed to save a context of said interrupted thread and modify the thread context before delivering the modified thread context to the operating system;

an exit handler that permits execution on resumption from the operating system following an entry through the entry handler, said exit handler obtained without modifying the operating system;

the exit handler programmed to restore the context saved by a corresponding execution of the entry handler; and

further comprising;

concurrent threads of control scheduled by the operating system, each thread having an associated context, an association between a thread and a set of computer resources of the associated context maintained by the operating system; and

the entry and exit handlers programmed to maintain an association between one of the threads and an extended context of the thread through a context change induced by the operating system, the extended context including resources of the computer associated with the thread that are beyond those resources whose association with the thread is maintained by the operating system.

59. The computer of claim 58, wherein the operating system is an operating system for a computer architecture other than the architecture native to the computer.

60. The computer of claim 58, having different execution modes of the computer for the operating system and the thread, and the association between the thread and the context is automatic, without an explicit software request, on a transition between the thread execution mode and the operating system execution mode.

61. The computer of claim 58, further comprising:

in the entry handler, memory saving a portion of the context of the computer, and a modifier for altering the context of the interrupted thread before delivering the interrupted thread and its corresponding context to the operating system.

62. The computer of claim 58, wherein the entry handler alters at least half of the data registers of the portion of a thread context maintained in association with the thread by the operating system before delivering the thread to the operating system.

63. The computer of claim 58, further comprising a linkage return address for the thread modified to include information used to maintain the association.

64. The computer of claim 59, which additionally executes an operating system native to the computer, and further comprising a classifier that determines the operating system for handling each interrupt or exception.

65. The computer of claim 59, wherein the operating system and the interrupted thread execute in different instruction set architectures of the computer.

75. The computer of claim 58:

wherein the interrupted thread at the point of interruption executes in one instruction set architecture and the operating system is coded primarily in a different instruction set architecture; and

further comprising a register set to a value that specifies actions to be taken by the entry handler or exit handler to convert operands from one form to another to conform to a data storage convention of the operating system instruction set architecture.

76. The computer of claim 58, further comprising either a delay deferring delivery of an interrupt before interrupting the thread by a time sufficient to allow the thread to reach a checkpoint in the execution of the thread where the amount of extended context, being the resources of the thread context beyond those whose resource association with the thread is maintained by the operating system, is reduced.

77. The computer of claim 58, further comprising either an operator for rolling execution of the thread back to a checkpoint in the execution of the thread where the amount of extended context, being the resources of the thread context beyond those whose resource association with the thread is maintained by the operating system, is reduced.

78. The computer of claim 58, further comprising either memory for storing at least the extended context, the extended context being the resources beyond those whose resource association with the thread is maintained by the operating system, into a storage location, a pool of storage locations being managed by a queuing discipline in which empty storage locations in which a context is to be saved are allocated from the head of a queue, recently-emptied storage locations for reuse are enqueued at the head of the queue, and full storage locations to be saved are queued at the tail of the queue.

66. A computer comprising:

an operating system;

an interrupted thread;

an entry handler that permits execution at a specified entry point or on a specified entry condition to the operating system, said entry handler obtained without modifying said pre-existing operating system of the computer;

said entry handler programmed to save a context of said interrupted thread and modify the thread context before delivering the modified thread context to the operating system;

an exit handler that permits execution on resumption from the operating system following an entry through the entry handler, said exit handler obtained without modifying the operating system;

the exit handler programmed to restore the context saved by a corresponding execution of the entry handler; and

further comprising; and

wherein the computer has different execution modes for the operating system and the thread, and the association between the thread and the context is automatic, without an explicit software request, on a transition between the thread execution mode and the operating system execution mode.

67. The computer of claim 66, wherein the thread execution mode and the operating system execution mode are two different instruction set architectures of the computer.

68. The computer of claim 66, wherein the operating system maintains an association between contexts and corresponding threads of execution, each such context including values of data registers, and further comprising:

a modifier modifying at least half of the data registers of the portion of the thread context maintained by the operating system before delivering the thread to the operating system.

69. The computer of claim 68, wherein at least some of the modified registers are overwritten by information indicating a storage location at which at least the portion of the thread context to be modified is saved before the modifying.

70. The computer of claim 68, wherein at least some of the modified registers are overwritten by a value that enables validation of the contents of the context.

71. The computer of claim 66, further comprising a linkage return address for the thread modified to include information used to maintain the association.

72. The computer of claim 71, wherein the linkage return address is modified with information indicating an execution path by which, or a condition on which, execution arrived at the entry handler.

73. The computer of claim 71, wherein the modification leaves at least half of the bits of the linkage return address intact.

74. The computer of claim 71, wherein the linkage return address is modified with information indicating a storage location at which at least the portion of the thread context to be modified is saved before the modifying.

79. A computer, comprising:

a service routine of said computer, a linkage return address passed to the service routine indicating the address at which to resume execution on completion of the service, the linkage return address deliberately chosen so that an attempt to execute an instruction from the linkage return address on return from the service routine will raise a program execution exception;

a processor attempting to execute the instruction at the linkage return address and raising the chosen exception, on return from the service routine; and

a controller returning control to a caller of the service routine, after servicing the exception.

80. The computer of claim 79, wherein the passed linkage return address points to a memory page having a memory attribute that raises the chosen exception on an attempt to execute an instruction from the page.

81. The computer of claim 79, wherein

the service routine is an interrupt service routine of an operating system for a computer architecture other than the architecture native to the computer;

the service routine is invoked by an asynchronous interrupt; and

the caller is coded in the instruction set native to the architecture.