TWO-DIMENSIONAL TIME DELAY INTEGRATION VISIBLE CMOS IMAGE SENSOR

• US 20080217661A1
• Filed: 03/08/2007
• Published: 09/11/2008
• Est. Priority Date: 03/08/2007
• Status: Active Grant

• Current Assignee: Teledyne Scientific & Imaging, LLC (Teledyne Technologies Incorporated)
• Original Assignee: Teledyne Licensing, LLC
• Inventors: Lauxtermann, Stefan
• Granted Patent: US 7,923,763 B2
• Time in Patent Office: Days
• US Class Current: 257/233
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H04N 25/711 Time delay and integration [TDI] registers; TDI shift registers
• CPC Class Codes: H04N 25/768 for time delay and integration [TDI]
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

A two dimensional time delay integration CMOS image sensor having a plurality of pinned photodiodes, each pinned photodiode collects a charge when light strikes the pinned photodiode, a plurality of electrodes separating the plurality of pinned photodiodes, the plurality of electrodes are configured for two dimensional charge transport between two adjacent pinned photodiodes, and a plurality of readout nodes connected to the plurality of pinned photodiodes via address lines.

Claims

1. A time delay integration CMOS image sensor comprising:

a first pinned photodiode and a second pinned photodiode, the first pinned photodiode collects a charge when light strikes the first pinned photodiode, the second pinned photodiode receives the charge from the first pinned photodiode; and

a plurality of electrodes in series located between the first and the second pinned photodiodes, the plurality of electrodes are configured to transfer the charge from the first pinned photodiode to the second pinned photodiode.

2. The time delay integration CMOS image sensor of claim 1 further comprising an address line and a readout node, the address line connects the readout node to the second pinned photodiode.

3. The time delay integration CMOS image sensor of claim 1 wherein the plurality of electrodes are activated consecutively at different cycles.

4. The time delay integration CMOS image sensor of claim 1 wherein the charge transfer occurs over a four cycle period.

5. A two dimensional time delay integration CMOS image sensor comprising:

an array of pinned photodiodes, each pinned photodiode is configured to collect a charge when light strikes the pinned photodiode; and

a plurality of electrodes located around the perimeter of each pinned photodiode to form a grid, the plurality of electrodes are configured to transport charge between two adjacent pinned photodiodes.

6. The two dimensional time delay integration CMOS image sensor of claim 5 further comprising a plurality of readout nodes coupled to the array of pinned photodiodes via address lines.

7. The two dimensional time delay integration CMOS image sensor of claim 5 further comprising a readout node for each pinned photodiode, the readout node is coupled to the array of pinned photodiodes via address line.

8. The two dimensional time delay integration CMOS image sensor of claim 5 wherein charge transport is bi-directional or tri-directional.

9. The two dimensional time delay integration CMOS image sensor of claim 5 wherein the grid is orthogonal or hexagonal.

10. The two dimensional time delay integration CMOS image sensor of claim 5 wherein the plurality of electrodes are activated consecutively at different cycles.

11. The two dimensional time delay integration CMOS image sensor of claim 5 wherein the charge transfer occurs over a four cycle period.

12. A two dimensional time delay integration CMOS image sensor comprising:

a plurality of pinned photodiodes, each pinned photodiode generates a charge when light strikes the pinned photodiode;

a plurality of electrodes separating the plurality of pinned photodiodes, the plurality of electrodes are configured for two dimensional charge transport between two adjacent pinned photodiodes; and

a plurality of readout nodes connected to the plurality of pinned photodiodes via address lines.

13. The two dimensional time delay integration CMOS image sensor of claim 12 wherein charge transport occurs in two or more directions.

14. The two dimensional time delay integration CMOS image sensor of claim 12 wherein the plurality of electrodes, the plurality of readout nodes and the address lines form a grid around the perimeter of each pinned photodiode

15. The two dimensional time delay integration CMOS image sensor of claim 14 wherein the grid is orthogonal or hexagonal.

16. The two dimensional time delay integration CMOS image sensor of claim 12 wherein the plurality of electrodes are activated consecutively at different cycles.

17. The two dimensional time delay integration CMOS image sensor of claim 12 wherein the charge transfer occurs over a four cycle period.

18. The two dimensional time delay integration CMOS image sensor of claim 12 wherein the number of readout nodes is equal to the number of pinned photodiodes.