Imaging apparatus, method, and system having reduced dark current

• US 20080217716A1
• Filed: 03/09/2007
• Published: 09/11/2008
• Est. Priority Date: 03/09/2007
• Status: Abandoned Application

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation), The Fiber Composite Company, Inc. (Smiths Group International Holdings Ltd.)
• Original Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Inventors: Mauritzson, Richard A.
• Application Number:
  US11/715,885
• Publication Number:
  US 20080217716A1
• Time in Patent Office: Days
• US Class Current: 257/443
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14698 Post-treatment for the devices, e.g. annealing, impurity-gettering, shor-circuit elimination, recrystallisation

Abstract

An imaging method, apparatus, and system having an image sensor having a p-type substrate to getter metallics and other contaminants, an n-type epitaxial layer arranged on the p-type substrate to reduce dark current, cross-talk, and blooming, and a p-type epitaxial layer arranged on the n-type epitaxial layer.

Claims

1. An imaging device, comprising:

a p-type substrate;

an n-type epitaxial arranged on substantially the entire p-type substrate;

a p-type epitaxial arranged on the n-epitaxial; and

a plurality of pixel circuits arranged in a pixel array region of the p-type epitaxial.

2. The imaging device of claim 1, wherein the p-type substrate is a p+ substrate.

3. The imaging device of claim 1, wherein the n-type epitaxial is an n−

epitaxial.

4. The imaging device of claim 1, wherein the p-type epitaxial is a p−

epitaxial.

5. The imaging device of claim 1, further comprising a polysilicon arranged under the p-type substrate.

6. The imaging device of claim 1, further comprising an n-type doped region arranged in the p-type epitaxial and coupled to a positive voltage source terminal for drawing electrons out of the n−

epitaxial.

7. The imaging device of claim 1, further comprising a p-type isolation implant region arranged in the p-type epitaxial and under the pixel array region.

8. The imaging device of claim 1, further comprising an n-type doped region arranged in the p-type epitaxial and surrounding the pixel array region.

9. The imaging device of claim 8, wherein the n-type doped region is coupled to a positive voltage source terminal for drawing electrons out of the n−

epitaxial.

10. The imaging device of claim 1, wherein the p-type substrate is doped to a resistivity of about 0.001 to about 0.05 Ω

-cm.

11. The imaging device of claim 1, wherein at least one of the p-epitaxial or n-epitaxial is doped to a resistivity of between about 10 to about 25 Ω

-cm.

13. The imaging device of claim 1, wherein the n−

epitaxial is between about 2 to about 6 μ

m thick.

14. The imaging device of claim 1, wherein the p−

epitaxial is between about 2 to about 8 μ

m thick.

34. The imaging device of claim 1, wherein the imaging device is included in a processor system.

35. The imaging device of claim 34, wherein the processor system is a camera.

12. (canceled)

15. An imaging device, comprising:

a p-type substrate;

an n-type epitaxial layer arranged on the p-type substrate;

a p-type epitaxial layer arranged on the n-epitaxial layer;

a CMOS pixel array comprising a plurality of pixel circuits arranged in the p-type epitaxial layer; and

a circuit for operating the CMOS pixel array to read out signals from the pixel circuits.

16. The imaging device of claim 15, further comprising a polysilicon layer arranged under the p-type substrate.

17. The imaging device of claim 15, further comprising an n-type doped region arranged in the p-type epitaxial layer and around the pixel array and coupled to a positive voltage source terminal.

18. The imaging device of claim 15, further comprising a p-type isolation implant region arranged in the p-type epitaxial layer and under the pixel array.

19. The imaging device of claim 15, wherein the p-type substrate is doped to a resistivity of about 0.001 to about 0.05 Ω

-cm, the p−

epitaxial layer is doped to a resistivity of between about 10 to about 25 Ω

-cm, and the n−

epitaxial layer is doped to a resistivity of between about 10 to about 25 Ω

-cm.

20. An imaging device, comprising:

a p-type substrate doped to a resistivity of about 0.001 to about 0.05 Ω

-cm;

an n-type epitaxial layer doped to a resistivity of between about 10 to about 25 Ω

-cm arranged on substantially the entire p-type substrate;

a p-type epitaxial layer doped to a resistivity of between about 10 to about 25 Ω

-cm arranged on the n-epitaxial layer;

a plurality of pixel circuits arranged in a pixel array region of the p-type epitaxial layer;

an n-type doped region arranged in the p-type epitaxial layer and surrounding the pixel array region and coupled to a positive voltage source terminal for drawing electrons out of the n−

epitaxial layer; and

a p-type isolation implant region arranged in the p-type epitaxial layer and under the pixel array region.

21. An imaging processing system, comprising:

a processor; and

an imaging device communicating with the processor, the device comprising;

a p+ doped substrate for gettering metallics;

an n−

epitaxial layer formed over the p+ doped substrate;

a p−

epitaxial layer formed over the n−

epitaxial layer;

a pixel array region having a plurality of pixels, the pixels having n-type doped photosensor regions arranged in the p−

epitaxial layer; and

a peripheral substrate region outside the pixel array region;

wherein the n−

epitaxial layer is on the p+ doped substrate in the pixel array region and in the peripheral substrate region.

22-27. -27. (canceled)

28. A method of making an imaging device, comprising:

doping a substrate to form a p-type doped substrate;

growing an n-type epitaxial layer on substantially the entire p-type doped substrate;

growing a p-type epitaxial layer on the n-type epitaxial layer; and

forming a plurality of pixels in a pixel array region, the pixels having n-type doped photosensor regions arranged in the p−

epitaxial layer.

29. The method of claim 28, wherein the p-type doped substrate is a p+ doped substrate, the n-type epitaxial layer is an n−

epitaxial layer, and the p-type epitaxial layer is a p−

epitaxial layer.

30. The method of claim 28, further comprising affixing a polysilicon layer to the p-type doped substrate.

31. The method of claim 28, further comprising doping the p-type epitaxial layer to form a p-type isolation implant region under the pixel array region.

32. The method of claim 28, further comprising doping the p-type epitaxial layer to form an n-type doped region around said plurality of pixels and coupling the n-type doped region to a positive voltage source terminal.

33. (canceled)