Open-Circuit Testing System and Method

• US 20080218175A1
• Filed: 05/02/2007
• Published: 09/11/2008
• Est. Priority Date: 03/08/2007
• Status: Active Grant

• Current Assignee: Test Research Incorporated
• Original Assignee: Test Research Incorporated
• Inventors: Chen, Chia-Ming, Chen, Chien-Wei
• Granted Patent: US 7,612,568 B2
• Time in Patent Office: Days
• US Class Current: 324/538
• CPC Class Codes: G01R 31/304 of printed or hybrid circuits G01R31/305 - G01R31/315 take precedence
• CPC Class Codes: G01R 31/312 by capacitive methods
• CPC Class Codes: G01R 31/70 Testing of connections between components and printed circuit boards G01R31/68 takes precedence

Abstract

The invention discloses a testing system and method suitable for determining the connection state of an electronic component in an electronic device assembly. In an embodiment, the testing system comprises a signal sensing unit configured to provide a sensed signal induced by capacitive coupling in response to the output of a testing signal passing through a tested pin, a signal processor unit configured to filter and over-sample the sensed signal to obtain a digital signal, and an analyzer unit configured to compute the digital signal for determining a connection state of the test pin.

Claims

1. A testing method for determining a connection state of an electronic component in an electronic device assembly, the method comprising:

obtaining a sensed signal induced by capacitive coupling in response to the output of a testing signal passing through a tested pin of the electronic component; and

applying a signal processing sequence on the sensed signal, the processing sequence including;

filtering and over-sampling the sensed signal to obtain a digital signal; and

computing the digital signal to determine the connection state of the tested pin.

2. The method according to claim 1, wherein the signal processing sequence includes amplifying the sensed signal before filtering the sensed signal.

3. The method according to claim 1, wherein the signal processing sequence includes processing the sensed signal through an anti-alias filter before over-sampling the sensed signal.

4. The method according to claim 1, wherein the signal processing sequence includes processing the digital signal through a digital filter before processing the digital signal to determine the connection state of the tested pin.

5. The method according to claim 4, wherein the digital filter includes a finite impulse response filter.

6. The method according to claim 1, further comprising applying a validation test to determine whether the sensed signal reflects the connection state of the tested pin.

7. The method according to claim 6, wherein applying the validation test comprises computing the digital signal to determine a correspondence with a predetermined capacitive coupling reference.

8. The method according to claim 7, further including raising a frequency and/or amplitude of the testing signal when the validation test determines no correspondence with the predetermined capacitive coupling reference.

9. The method according to claim 8, wherein the sensed signal does not reflect the connection state of the tested pin when the validation test determines no correspondence with the predetermined capacitive coupling reference.

10. The method according to claim 8, further comprising:

obtaining a new sensed signal corresponding to the testing signal of raised frequency and/or amplitude; and

applying the signal processing sequence for the new sensed signal to determine the connection state of the tested pin.

11. The method according to claim 1, wherein processing the digital signal to determine the connection state of the tested pin includes applying a Fast Fourier Transform to convert the digital signal into a frequency-domain spectrum data.

20. The system according to claim 11, wherein the analyzer unit is configured to apply a Fast Fourier Transform to convert the digital signal into frequency-domain spectrum data for determining the connection state of the tested pin.

12. A testing system suitable for determining a connection state of an electronic component in an electronic device assembly, the testing system comprising:

a signal sensing unit configured to provide a sensed signal induced by capacitive coupling in response to the output of a testing signal passing through a tested pin of the electronic component;

a signal processor unit configured to filter and over-sample the sensed signal to obtain a digital signal; and

an analyzer unit configured to compute the digital signal for determining a connection state of the test pin.

13. The system according to claim 12, wherein the signal processor unit includes an anti-alias filter through which the sensed signal is processed before being over-sampled.

14. The system according to claim 12, wherein the signal processor unit includes a digital filter through which the digital signal is processed before being converted into frequency-domain spectrum data.

15. The system according to claim 14, wherein the digital filter includes a finite impulse response filter.

16. The system according to claim 12, wherein the analyzer unit is further configured to perform a validation test to determine whether the sensed signal reflects the connection state of the tested pin.

17. The system according to claim 16, wherein the validation test comprises computing the digital signal to determine a correspondence with a predetermined capacitive coupling reference.

18. The system according to claim 17, further including a controller configured to raise a frequency and/or amplitude of the testing signal when the validation test determines no correspondence with the predetermined capacitive coupling reference.

19. The system according to claim 18, wherein the sensed signal does not reflect the connection state of the tested pin when the validation test determines no correspondence with the predetermined capacitive coupling reference.