Programmable logic integrated circuit for digital algorithmic functions
First Claim
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1. An integrated circuit comprising:
- an integrated circuit programmable to operate on input data in accordance with one or more predetermined digital algorithms comprising;
a first memory portion comprising at least one instruction defining a digital algorithm;
a second memory portion comprising configuration data in conjunction with said digital algorithm;
a third memory portion operable to selectively provide data inputs and to receive and store data outputs;
a logic computation unit comprising a programmable array of a plurality of execution units, each of said execution units being programmable to provide Boolean functionality as determined by a corresponding first portion of said one instruction, each of said execution units being programmably interconnected with others of said execution units in accordance with said at least a portion of said configuration data, and each of said execution units programmably operating on data inputs from said third memory portion to provide said data outputs for storage in said third memory portion;
and a circuit operable to provide execution clock cycles to said first, second and third memory portions such that said logic computation unit computes said digital algorithm, said execution clock cycles being selected such that the time to compute said digital algorithm is a predetermined time.
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Abstract
A programmable integrated circuit for calculating a digital algorithm is disclosed. The integrated circuit is programmable to operate on input data in accordance with one or more predetermined digital algorithms.
53 Citations
31 Claims
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1. An integrated circuit comprising:
an integrated circuit programmable to operate on input data in accordance with one or more predetermined digital algorithms comprising; a first memory portion comprising at least one instruction defining a digital algorithm; a second memory portion comprising configuration data in conjunction with said digital algorithm; a third memory portion operable to selectively provide data inputs and to receive and store data outputs; a logic computation unit comprising a programmable array of a plurality of execution units, each of said execution units being programmable to provide Boolean functionality as determined by a corresponding first portion of said one instruction, each of said execution units being programmably interconnected with others of said execution units in accordance with said at least a portion of said configuration data, and each of said execution units programmably operating on data inputs from said third memory portion to provide said data outputs for storage in said third memory portion; and a circuit operable to provide execution clock cycles to said first, second and third memory portions such that said logic computation unit computes said digital algorithm, said execution clock cycles being selected such that the time to compute said digital algorithm is a predetermined time. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. An integrated circuit comprising:
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an integrated circuit programmable to operate on input data in accordance with one or more predetermined digital algorithms comprising; a logic computation unit comprising a plurality of execution elements, each execution element being selectively programmable to operate on input data to generate output data having a predetermined Boolean logic relationship to said input data; an instruction memory comprising at least one instruction defining a digital algorithm, said instruction memory coupled to said logic computation unit to provide a controlled instruction stream to said logic computation unit, said controlled instruction stream controlling said predetermined Boolean logic relationship for each of said execution units; a state memory coupled to said logic computation unit to selectively provide data inputs to said logic computation unit and to receive outputs from said logic computation unit; a circuit coupled to said instruction memory to provide an instruction pointer and coupled to said state memory to control selection of data inputs to said logic computation unit from said state memory and to control selection of outputs from said logic computation unit for storage in said state memory. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A method for providing an integrated circuit for computing one or more digital algorithms, comprising:
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generating an instruction stream for a digital algorithm to be compiled into logic gates; providing a first memory on said integrated circuit; mapping said instruction stream into a first memory; providing a second memory on said integrated circuit; storing configuration data in conjunction with said digital algorithm in said second memory; providing a third memory on said integrated circuit to selectively provide data inputs and to receive and store data outputs; providing a logic computation unit on said integrated circuit, said logic computation unit comprising a programmable array of a plurality of execution units, each of said units being programmable to provide Boolean functionalities as determined by said instruction stream, each of said units being programmably interconnected with others of said units in accordance with said configuration data and each of said units programmably operating on data inputs from said third memory to provide said data outputs for storage in said third memory; providing execution clock cycles; providing input data to said logic computation unit from said third memory during each of said execution clock cycles; providing said instruction stream to said logic computation unit from said first memory during each of said execution cycles; providing said configuration data to said logic computation unit from said second memory during each of said execution cycles; and storing output data from said logic computation unit in said third memory during each of said execution cycles. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31)
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Specification