Timing Exact Design Conversions from FPGA to ASIC

• US 20080218205A1
• Filed: 04/16/2008
• Published: 09/11/2008
• Est. Priority Date: 07/08/2002
• Status: Active Grant

• Current Assignee: Liberty Patents LLC
• Original Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Inventors: Madurawe, Raminda Udaya
• Granted Patent: US 8,499,269 B2
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks
• CPC Class Codes: H10B 10/10 SRAM devices comprising bipolar components

Abstract

A device having a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC), comprising: a user configurable element in the FPGA replaced by a mask configurable element in the ASIC, wherein the FPGA and the ASIC have identical die size and identical transistor layouts.

Claims

1. A device comprising a field programmable gate array (FPGA) and an application specific integrated circuit (ASIC), wherein a design implemented in either the FPGA or the ASIC comprises identical timing, the device comprised of:

a programmable logic circuit having an identical layout in the FPGA and the ASIC; and

a random access memory (RAM) element to program the logic circuit in the FPGA; and

a read only memory (ROM) conductive element to program the logic circuit in the ASIC, wherein the RAM value is duplicated to the ROM value to identically program the programmable logic circuit.

2. The device of claim 1, further comprising a routing structure having metal and via interconnects, the routing structure having an identical layouts in the FPGA and the ASIC.

3. The device of claim 1, wherein in the ASIC, the ROM element comprises a metal link coupled to a power supply voltage or a ground supply voltage.

4. The device of claim 1, further comprising a user configurable configuration circuit in the FPGA to program the RAM element to a user specification.

5. The device of claim 1, further comprising a mask configurable configuration circuit in the ASIC to program the ROM element to a user specification.

6. The device of claim 1, wherein the ASIC fabrication comprises a cost reduction by the elimination of RAM construction process steps associated with the FPGA fabrication.

7. The device of claim 1, wherein the ASIC fabrication comprises a data disturb based reliability improvement by the replacement of a RAM element in the FPGA by a hard-wired ROM elements in the ASIC.

8. The device of claim 1, wherein the FPGA further comprises:

one or more digital circuits formed on a silicon substrate;

one or more programmable logic blocks formed on the silicon substrate layer and electrically coupled to the digital circuits;

one or more memory blocks formed on the silicon substrate layer and electrically coupled to the digital circuits and the programmable logic blocks; and

one or more user configurable RAM elements formed above or below the silicon substrate layer and electrically coupled to the programmable logic blocks to customize the programmable content of the FPGA.

9. The device of claim 1, wherein the RAM element further comprising one of:

a fuse link, an anti-fuse capacitor, an SRAM cell, a DRAM cell, a metal optional link, an EPROM cell, an EEPROM cell, a flash cell, a ferro-electric element, an electro-chemical cell, an electromagnetic cell, a carbon nano-tube, an optical element and a magnetic element.

10. The device of claim 1, wherein the ASIC further comprises:

one or more digital circuits formed on a silicon substrate;

one or more programmable logic blocks formed on the silicon substrate layer and electrically coupled to the digital circuits;

one or more memory blocks formed on the silicon substrate layer and electrically coupled to the digital circuits and the programmable logic blocks; and

one or more mask configurable ROM elements formed above or below the silicon substrate layer and electrically coupled to the programmable logic blocks to customize the programmable content of the ASIC.

11. A field programmable gate array (FPGA) design conversion to an application specific integrated circuit (ASIC), comprising:

providing an FPGA device and an ASIC device having;

a substantially identical die size; and

a substantially identical transistors and one or more metal layer layouts; and

providing a user configurable memory to program transistors in the FPGA; and

providing a mask configurable memory to program transistors in the ASIC; and

converting a user configurable memory bit pattern generated by a software tool to program the transistors of the FPGA to a mask configurable metal pattern to identically program the transistors of the ASIC.

12. The conversion of claim 11, wherein digital circuits in the FPGA are identical to digital circuits in the ASIC.

13. The conversion of claim 11, wherein interconnects and routing in the FPGA are identical to interconnects and routing in the ASIC.

14. The conversion of claim 11, wherein control signals to program the programmable logic content in the FPGA are identical to control signals to program the programmable logic content in the ASIC.

15. The conversion of claim 14, wherein the user configurable memory generate the control signals in the FPGA, and wherein the mask configurable metal generate the control signals in the ASIC.

16. The conversion of claim 11, wherein the FPGA and the ASIC further comprises:

an input, said input received at an input-pad; and

an output, said output generated at an output-pad;

wherein, an input to output signal propagation delay is substantially identical between the FPGA and the ASIC.

17. The conversion of claim 11, wherein the memory element in the FPGA further comprising one of:

a fuse link, an anti-fuse capacitor, an SRAM cell, a DRAM cell, a metal optional link, an EPROM cell, an EEPROM cell, a flash cell, a ferro-electric element, an electro-chemical cell, an electromagnetic cell, a carbon nano-tube, an optical element and a magnetic element.

18. The conversion of claim 11, wherein the mask configurable metal in the ASIC further comprises a metal wire coupled to a power supply voltage or a ground supply voltage.

19. A device having a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC), comprising:

a user configurable element in the FPGA replaced by a mask configurable element in the ASIC, wherein the FPGA and the ASIC have identical die size and identical transistor layouts.

20. The conversion of claim 19, wherein the FPGA and the ASIC comprises substantially identical functionality and timing characteristics.