Apparatus and method for operating a phase-locked loop circuit

• US 20080218277A1
• Filed: 05/30/2007
• Published: 09/11/2008
• Est. Priority Date: 03/08/2007
• Status: Active Grant

• Current Assignee: O2 Micro International Limited (O2 Micro Incorporated)
• Original Assignee: O2 Micro International Limited (O2 Micro Incorporated)
• Inventors: Tan, Seeteck, Chu, Meng
• Granted Patent: US 7,633,347 B2
• Time in Patent Office: Days
• US Class Current: 331/17
• CPC Class Codes: H03L 2207/04 Modifications for maintaining constant the phase-locked loop damping factor when other loop parameters change
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

An apparatus and method for operating a phase-locked loop circuit are disclosed. The phase locked loop circuit includes a plurality of resistive elements and a plurality of capacitive elements that are distributed in a charge pump, a loop filter and a voltage controlled oscillator. The plurality of resistive elements have a plurality of resistances that vary in proportion to each other. The plurality of capacitive elements have a plurality of capacitive elements that vary in proportion to each other. A damping factor of the phase-locked loop circuit is maintained substantially constant by the plurality of resistive elements and the plurality of capacitive elements.

Claims

1. A phase-locked loop circuit with a loop path, said loop path comprising:

a charge pump with a charge resistor section for generating a charge pump current;

a loop filter with a filter resistor section and a filter capacitor section coupled to said charge pump for generating an oscillator control voltage based on said charge pump current; and

a voltage controlled oscillator with an oscillator resistor section and an oscillator capacitor section coupled to said loop filter for generating an output clock under control of said oscillator control voltage,

wherein the resistance of said filter resistor section varies in proportion to both the resistance of said charge resistor section and the resistance of said oscillator resistor section, and the capacitance of said filter capacitor section varies in proportion to the capacitance of said oscillator capacitor section to maintain a damping factor of said phase-locked loop circuit substantially constant.

2. The phase-locked loop circuit of claim 1, wherein said charge resistor section, said filter resistor section and said oscillator resistor section comprise a plurality of resistive elements of the same type, and said filter capacitor section and said oscillator capacitor section comprise a plurality of capacitive elements of the same type.

3. The phase-locked loop circuit of claim 2, wherein said resistive elements each comprise a switchable resistor array with adjustable resistance.

4. The phase-locked loop circuit of claim 2, wherein said capacitive elements each comprise a switchable capacitor array with adjustable capacitance.

5. The phase-locked loop circuit of claim 1, wherein said damping factor is substantially constant irrespectively of manufacturing process and operation environments.

6. The phase-locked loop circuit of claim 1, wherein a RC product of said resistance of said charge resistor section, said resistance of said oscillator resistor section, said capacitance of said filter capacitor section and said capacitance of said oscillator capacitor section is kept constant to maintain a natural frequency of said phase-locked loop circuit substantially constant.

7. The phase-locked loop circuit of claim 6, wherein said natural frequency is substantially constant irrespectively of manufacturing process and operation environments.

8. The phase-locked loop circuit of claim 6, further comprising:

a tuning circuit coupled to said loop path for maintaining said natural frequency substantially constant.

9. The phase-locked loop circuit of claim 8, wherein said tuning circuit further comprises:

a current source with a tuning resistor for generating a tuning current;

a tuning capacitor charged by said tuning current and generating a tuning voltage; and

a tuning signal generator coupled to said tuning capacitor for generating a tuning signal based on said tuning voltage.

10. The phase-locked loop circuit of claim 9, wherein said tuning signal is applied to adjust resistances of said tuning resistor, said charge resistor section, said filter resistor section and said oscillator resistor section.

11. The phase-locked loop circuit of claim 9, wherein said tuning signal is applied to adjust resistances of said tuning capacitor, said filter capacitor section and said oscillator capacitor section.

12. The phase-locked loop circuit of claim 9 wherein said tuning resistor is of the same type as resistive elements in said charge resistor section, said filter resistor section and said oscillator resistor section, and said tuning capacitor is of the same type as capacitive elements in said filter capacitor section and said oscillator capacitor section.

13. The phase-locked loop circuit of claim 9, wherein said tuning signal generator further comprises:

a switch coupled in parallel with said tuning capacitor, wherein said tuning capacitor is charged during a predetermined off period of said switch and discharged during an on period of said switch;

a comparator coupled to said tuning capacitor for comparing said tuning voltage with a reference voltage and generating an output signal based on a result of said comparing; and

a digital block coupled to said comparator for generating said tuning signal based on a reference clock signal and said output signal, wherein said digital block is further coupled to said switch for predetermining said off period.

14. The phase-locked loop circuit of claim 13, wherein said predetermined off period is longer than a period used for said tuning voltage to attain said reference voltage.

15. The phase-locked loop circuit of claim 1, wherein said charge pump further comprises a current mirror with a programmable mirror gain, and wherein said programmable mirror gain is predetermined according to said output clock to maintain said damping factor substantially constant when the frequency of said output clock varies.

16. The phase-locked loop circuit of claim 1, wherein said voltage controlled oscillator further comprises a current mirror with a programmable mirror gain, and wherein said programmable mirror gain is predetermined according to said output clock to maintain said damping factor substantially constant when the frequency of said output clock varies.

17. The phase-locked loop circuit of claim 1, wherein said voltage controlled oscillator is a ring oscillator realized by a plurality of inverters coupled in cascade.

18. The phase-locked loop circuit of claim 1, wherein said charge pump further comprises:

a reference current generator for generating a reference current;

a current mirror coupled to said reference current generator for generating said charge pump current based on said reference current; and

a switch device coupled to said current mirror for determining a flowing direction of said charge pump current according to a control signal.

19. The phase-locked loop circuit of claim 1, wherein said voltage controlled oscillator further comprises:

a current source for generating a plurality of currents;

a plurality of oscillator capacitors coupled to said current source for generating a plurality of oscillator voltages by selectively charging said plurality of oscillator capacitors with said plurality of currents;

a comparator coupled to said plurality of oscillator capacitors for comparing said plurality of oscillator voltages with a reference voltage; and

a flip-flop coupled to said comparator for generating said output clock based on a result of said comparing, wherein said output clock further controls the charging of said plurality of oscillator capacitors.

20. The phase-locked loop circuit of claim 1, wherein said phase-locked loop circuit is selected from the group consisting of:

a second order circuit;

a third order circuit; and

a fourth order circuit.

21. A method for operating a phase-locked loop circuit, comprising:

comparing a reference clock with a feedback clock and generating a control signal based on a result of said comparing;

generating an output clock based on said control signal in a loop path comprising a plurality of resistive elements and a plurality of capacitive elements, wherein the resistances of said resistive elements vary in proportion to each other, the capacitances of said capacitive elements vary in proportion to each other, and a damping factor of said phase-looked loop circuit is maintained substantially constant by using said plurality of resistive elements and said plurality of capacitive elements; and

generating said feedback clock by dividing said output clock by a divider factor.

22. The method of claim 21, wherein said plurality of resistive elements are of the same type and said plurality of capacitive elements are of the same type.

23. The method of claim 21, further comprising

adjusting said plurality of resistive elements to maintain a natural frequency of said phase-locked loop circuit substantially constant.

24. The method of claim 21, further comprising

adjusting said plurality of capacitive elements to maintain a natural frequency of said phase-locked loop circuit substantially constant.

25. The method of claim 21, further comprising:

generating a tuning current using a tuning resistor;

charging a tuning capacitor with said tuning current to generate a tuning voltage; and

generating a tuning signal based on said tuning voltage.

26. The method of claim 25, wherein said tuning resistor is of the same type as said plurality of resistive elements and said tuning capacitor is of the same type as said plurality of capacitive elements.

27. The method of claim 25, further comprising:

applying said tuning signal to said tuning resistor and said plurality of resistive elements; and

adjusting said tuning resistor and said plurality of resistive elements according to said tuning signal to cause the resistance of said tuning resistor to vary in inverse proportion to the capacitance of said tuning capacitor such that said plurality of resistances vary in inverse proportion to said plurality of capacitances.

28. The method of claim 25, further comprising:

applying said tuning signal to said tuning capacitor and said plurality of capacitive elements; and

adjusting said tuning capacitor and said plurality of capacitive elements according to said tuning signal to cause the capacitance of said tuning capacitor to vary in inverse proportion to the resistance of said tuning resistor such that said plurality of capacitances vary in inverse proportion to said plurality of resistances.

29. The method of claim 21, further comprising:

adjusting a mirror gain of said phase-locked loop circuit to maintain said damping factor substantially constant when an output clock of said phase-locked loop circuit varies, wherein said mirror gain is realized between loop currents.

30. The method of claim 29, wherein said mirror gain is adjusted by a digital selection signal that is predetermined according to the frequency of said output clock.

31. A system for operating a phase-locked loop circuit, comprising:

a frequency phase detector for comparing a reference clock with a feedback clock and generating a control signal based on a result of said comparing;

a loop path with a plurality of resistive elements and a plurality of capacitive elements coupled to said frequency phase detector for generating an output clock based on said control signal, wherein the resistances of said resistive elements vary in proportion to each other, the capacitances of said capacitive elements vary in proportion to each other, and a damping factor of said phase-looked loop circuit is maintained substantially constant by using said plurality of resistive elements and said plurality of capacitive elements; and

a frequency divider coupled to said loop path for generating said feedback clock by dividing said output clock by a divider factor.

32. The system of claim 31, wherein said plurality of resistive elements are of the same type and said plurality of capacitive elements are of the same type.

33. The system of claim 31, wherein said loop path has a mirror gain realized between loop currents, and wherein said mirror gain is adjusted according to said output clock to maintain said damping factor substantially constant when the frequency of said output clock varies.

34. The system of claim 31, further comprising:

a tuning circuit coupled to said loop path for causing said resistances of said resistive elements to vary in inverse proportion to said capacitances of said capacitive elements to maintain a natural frequency of said phase-locked circuit substantially constant.

35. The system of claim 34, wherein said tuning circuit comprises a tuning resistor and a tuning capacitor, and wherein said tuning resistor is of the same type as said plurality of resistive elements and said tuning capacitor is of the same type as said plurality of capacitive elements.