High intrascene dynamic range NTSC and PAL imager

• US 20080218621A1
• Filed: 04/14/2008
• Published: 09/11/2008
• Est. Priority Date: 08/29/2002
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Barna, Sandor L., Subbotin, Igor, Kaplinsky, Michael, Cho, Kwang-Bo, Slayton, Gary E.
• Granted Patent: US 7,973,842 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H04N 23/70 Circuitry for compensating brightness variation in the scene
• CPC Class Codes: H04N 23/741 by increasing the dynamic range of the image compared to the dynamic range of the electronic image sensors
• CPC Class Codes: H04N 25/583 with different integration times
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

The invention provides a new method and apparatus for NTSC and PAL image sensors which employs fusion of adjacent row pixel charge samples to generate image data for a row. A variety of fusion schemes are possible for fusing the pixel signals from the adjacent rows. The rows of pixels are scanned so that each scan takes an odd row signal sample and, in some cases, an adjacent even row signal sample when specified conditions are met. One sampled row of the two adjacent rows integrate an image with a first integration period while the other adjacent row integrates an image with a second integration period.

Claims

1. A pixel imager comprising:

a first pixel circuit in a first pixel row for outputting at least a first pixel image signal accumulated during a first integration period;

a second pixel circuit in a second pixel row for outputting at least a second pixel image signal accumulated during a second integration period which is shorter than said first integration period; and

a sample and hold circuit for selectively acquiring at least one of said first and second pixel image signals and for outputting a pixel output signal which is based on at least one of (1) an average of said first and second pixel signals and (2) a selection of one of said first and second pixel image signals based on a value of said first pixel image signal.

2-42. -42. (canceled)