Read Disturb Reduction Circuit for Spin Transfer Torque Magnetoresistive Random Access Memory

• US 20080219044A1
• Filed: 06/29/2007
• Published: 09/11/2008
• Est. Priority Date: 03/06/2007
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Kang, Seung H., Yoon, Sei Seung, Sani, Medi Hamidi
• Granted Patent: US 8,004,880 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/067 Single-ended amplifiers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

Systems, circuits and methods for reducing read disturbances in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A resistive element can be used during the read operation to control the read current and control read disturbances. An isolation element can be used to isolate the resistive element from the circuit during write operations.

Claims

1. A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) comprising:

a bit cell coupled to a bit line and a source line; and

a resistive element interposed between the bit cell and a sense amplifier in the bit line.

2. The STT-MRAM of claim 1, further comprising:

an isolation element couple to the resistive element and interposed between the bit cell and the sense amplifier, wherein the isolation element is configured to selectively couple the resistive element to the bit line during a read operation.

3. The STT-MRAM of claim 2, wherein the isolation element and resistive element are coupled in series in the bit line.

4. The STT-MRAM of claim 1, wherein the isolation element is at least one of a transistor, switch, a transmission gate, or a multiplexer.

5. The STT-MRAM of claim 1, wherein the resistive element is at least one of a poly, an active, a well or a transistor device.

6. The STT-MRAM of claim 1, wherein the bit cell comprises:

a magnetic tunnel junction (MTJ); and

a word line transistor coupled in series with the MTJ.

7. The STT-MRAM of claim 1, further comprising:

a first pre-charge transistor coupled to the resistive element, wherein the first pre-charge transistor is configured to provide a positive voltage to the bit line during a read operation.

8. The STT-MRAM of claim 7, further comprising:

a second pre-charge transistor couple to the bit line; and

a third pre-charge transistor coupled to the source line.

9. The STT-MRAM of claim 8, wherein the second pre-charge transistor is configured to discharge the bit line prior to the read operation and the third pre-charge transistor is configured to discharge the source line.

10. The STT-MRAM of claim 1, further comprising:

a write driver configured to store a logic state in the bit cell; and

two write isolation elements coupled in series with the write driver between the bit line and source line, wherein the write isolation elements are configured to couple the write driver to the bit line and source line during a write operation.

11. The STT-MRAM of claim 10, wherein the write driver is configured to differentially drive the bit line and source line.

12. The STT-MRAM of claim 11, wherein the write driver comprises:

first and second inverters coupled in series between a data input and the bit line; and

a third inverter coupled in series between the data input and the source line.

13. The STT-MRAM of claim 1, further comprising:

a reference source; and

a reference resistive element coupled between the reference source and the sense amplifier.

14. The STT-MRAM of claim 1, further comprising:

a plurality of bit cells coupled to the bit line and the source line, wherein the resistive element is interposed between the plurality of bit cells and the sense amplifier in the bit line.

15. A method for preventing read disturbances in a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) comprising:

coupling a resistive element between a bit cell and a sense amplifier during a read operation; and

decoupling the resistive element during a write operation.

16. The method of claim 15, wherein the bit cell is coupled to a bit line and source line and the resistive element is in series in the bit line.

17. The method of claim 16, further comprising:

charging the bit line before reading the bit line;

reading the bit line after the charge has stabilized; and

discharging the source line before reading the bit line.

18. The method of claim 15, further comprising:

generating a read enable signal that controls the coupling and decoupling of the resistive element.

19. The method of claim 18, wherein an isolation element receives the read enable signal and is configured to couple the resistive element during a read operation and decouple the resistive element during a write operation.

20. The method of claim 15, wherein the bit cell comprises:

a magnetic tunnel junction (MTJ); and

a word line transistor coupled in series with the MTJ.

21. The method of claim 15, further comprising:

generating a bit line reference source;

determining a logic state of the bit cell based upon the difference between the bit line and the reference source at the sense amplifier, wherein a reference resistive element is coupled between the reference source and the sense amplifier.