REDUCTION OF BACK PATTERN DEPENDENCY EFFECTS IN MEMORY DEVICES

• US 20080219050A1
• Filed: 02/26/2008
• Published: 09/11/2008
• Est. Priority Date: 01/24/2007
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Shalvi, Ofir, Cohen, Zeev
• Granted Patent: US 8,151,166 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS

Abstract

A method for operating a memory that includes multiple analog memory cells includes storing data in the memory by writing first storage values to the cells, so as to cause the cells to hold respective electrical charge levels. After storing the data, second storage values are read from at least some of the cells, including at least one interfered cell that belongs to a group of cells. A Back Pattern Dependency (BPD) distortion caused by the electrical charge levels of one or more interfering cells in the group to at least one of the second storage values read from the at least one interfered cell is detected and canceled. The second storage values, including the at least one of the second storage values in which the BPD distortion was canceled, are processed so as to reconstruct the data.

Claims

1. A method for operating a memory that includes multiple analog memory cells, the method comprising:

storing data in the memory by writing first storage values to the cells, so as to cause the cells to hold respective electrical charge levels;

after storing the data, reading second storage values from at least some of the cells, including at least one interfered cell that belongs to a group of cells;

detecting and canceling a Back Pattern Dependency (BPD) distortion caused by the electrical charge levels of one or more interfering cells in the group to at least one of the second storage values read from the at least one interfered cell; and

processing the second storage values, including the at least one of the second storage values in which the BPD distortion was canceled, so as to reconstruct the data.

2. The method according to claim 1, wherein the analog memory cells comprise NAND Flash cells, and wherein the group of cells comprises a NAND string.

3. The method according to claim 1, wherein detecting and canceling the BPD distortion comprise evaluating a condition indicating that the interfered cell is likely to be subject to the BPD distortion, and canceling the BPD distortion responsively to the evaluated condition.

4. The method according to claim 3, wherein storing the data comprises encoding the data with an error detection code, and wherein evaluating the condition comprises decoding the error detection code and identifying a data error using the decoded error detection code.

5. The method according to claim 3, wherein reading the second storage values comprises processing the read second storage values so as to identify one or more over-programmed cells among the memory cells in the memory, and wherein evaluating the condition comprises determining that the group of cells comprises at least one of the over-programmed cells.

6. The method according to claim 1, wherein detecting and canceling the BPD distortion comprise recursively estimating a part of the BPD distortion in a given cell in the group based on one or more other parts of the BPD distortion in respective one or more cells in the group that were programmed earlier than the given cell, and on the second storage values that were read from the one or more cells.

7. The method according to claim 6, wherein estimating the part of the BPD distortion comprises measuring a total BPD distortion that is caused by the cells in the group, and estimating the part of the BPD distortion based on the total BPD distortion.

8. The method according to claim 7, wherein the cells in the group are connected in series to one another, and wherein measuring the total BPD distortion comprises applying pass voltages to respective gates of the cells in the group and measuring a current flowing through the cells responsively to the applied pass voltages.

9. The method according to claim 1, wherein the cells in the group are connected in series to one another, wherein reading the second storage value from the interfered cell comprises applying a read voltage to a gate of the interfered cell, applying pass voltages to respective gates of the other cells in the group and measuring a current flowing through the cells responsively to the applied read voltage and pass voltages, and wherein canceling the BPD distortion comprises increasing at least one of the pass voltages and reading the second storage value from the interfered cell using the increased pass voltages.

10. The method according to claim 9, wherein increasing the pass voltages comprises increasing the pass voltages of only a subset of the cells in the group that were programmed later than the interfered cell.

11. The method according to claim 9, wherein increasing the pass voltages comprises increasing the pass voltages iteratively until meeting a condition indicating that the BPD distortion is canceled.

12. The method according to claim 11, wherein increasing the pass voltages comprises storing the pass voltages for which the condition was met, and applying the stored pass voltages when performing a subsequent read operation on the group of cells.

13. The method according to claim 9, and comprising, after reading the second storage value from the interfered cell using the increased pass voltages, copying the data stored in the group to another group of the memory cells.

14. The method according to claim 9, wherein reading the second storage value from the interfered cell comprises reading the second storage value multiple times while applying respective different values of the pass voltages to the gates of the other cells in the group, and wherein canceling the BPD distortion comprises selecting one of the read second storage values having a lowest level of the BPD distortion.

15. The method according to claim 1, wherein the cells in the group are connected in series to one another, wherein reading the second storage value from the interfered cell comprises applying a read voltage to a gate of the interfered cell, applying pass voltages to respective gates of the other cells in the group and measuring a current flowing through the cells responsively to the applied read voltage and pass voltages, and wherein canceling the BPD distortion comprises reducing at least one of the pass voltages while not violating a predefined performance criterion, and reading the second storage value from the interfered cell using the reduced pass voltages.

16. The method according to claim 1, wherein reading the second storage values comprises processing the read second storage values so as to identify one or more over-programmed cells among the memory cells in the memory and storing information regarding the identified over-programmed cells, and wherein canceling the BPD distortion comprises processing the stored information regarding the over-programmed cells with regard to the read second storage values so as to cancel the BPD distortion.

17. The method according to claim 16, wherein processing the stored information comprises estimating the BPD distortion based on the stored information and subtracting the estimated BPD distortion from the second storage value read from the interfered cell.

18. The method according to claim 16, wherein storing the data comprises encoding the data with an Error Correction Code (ECC), wherein processing the stored information comprises calculating metrics for decoding the ECC based on the stored information, and wherein processing the second storage values so as to reconstruct the data comprises decoding the ECC responsively to the metrics.

19. The method according to claim 1, wherein detecting the BPD distortion comprises measuring shifts in one or more of the second storage values read from a subset of the cells in the group, which occurred after the cells were programmed, and estimating the BPD distortion responsively to the measured shifts.

20. The method according to claim 1, wherein storing the data comprises encoding the data with an Error Correction Code (ECC), wherein canceling the BPD distortion comprises computing metrics for decoding the ECC based on the detected BPD distortion, and wherein processing the second storage values so as to reconstruct the data comprises decoding the ECC responsively to the metrics.

21. A data storage apparatus, comprising:

an interface, which is operative to communicate with a memory that includes multiple analog memory cells; and

a processor, which is coupled to store data in the memory by writing first storage values to the cells so as to cause the cells to hold respective electrical charge levels, to read, after storing the data, second storage values from at least some of the cells, including at least one interfered cell that belongs to a group of cells, to detect and cancel a Back Pattern Dependency (BPD) distortion caused by the electrical charge levels of one or more interfering cells in the group to at least one of the second storage values read from the at least one interfered cell, and to process the second storage values, including the at least one of the second storage values in which the BPD distortion was canceled, so as to reconstruct the data.

22. The apparatus according to claim 21, wherein the analog memory cells comprise NAND Flash cells, and wherein the group of cells comprises a NAND string.

23. The apparatus according to claim 21, wherein the processor is coupled to evaluate a condition indicating that the interfered cell is likely to be subject to the BPD distortion, and to cancel the BPD distortion responsively to the evaluated condition.

24. The apparatus according to claim 23, wherein the processor is coupled to encode the data with an error detection code and to decode the error detection code when reconstructing the data, and wherein the condition checks whether a data error is identified by the decoded error detection code.

25. The apparatus according to claim 23, wherein the processor is coupled to process the read second storage values so as to identify one or more over-programmed cells among the memory cells in the memory, and wherein the condition checks whether the group of cells comprises at least one of the over-programmed cells.

26. The apparatus according to claim 21, wherein the processor is coupled to recursively estimate a part of the BPD distortion in a given cell in the group based on one or more other parts of the BPD distortion in one or more cells in the group that were programmed earlier than the given cell, and on the second storage values that were read from the one or more cells.

27. The apparatus according to claim 26, wherein the processor is coupled to estimate the part of the BPD distortion by measuring a total BPD distortion that is caused by the cells in the group, and estimating the part of the BPD distortion based on the total BPD distortion.

28. The apparatus according to claim 27, wherein the cells in the group are connected in series to one another, and wherein the processor is coupled to measure the total BPD distortion by applying pass voltages to respective gates of the cells in the group and measuring a current flowing through the cells responsively to the applied pass voltages.

29. The apparatus according to claim 21, wherein the cells in the group are connected in series to one another, wherein the processor is coupled to read the second storage value from the interfered cell by applying a read voltage to a gate of the interfered cell, applying pass voltages to respective gates of the other cells in the group and measuring a current flowing through the cells responsively to the applied read voltage and pass voltages, and to cancel the BPD distortion by increasing at least one of the pass voltages and reading the second storage value from the interfered cell using the increased pass voltages.

30. The apparatus according to claim 29, wherein the processor is coupled to increase the pass voltages of only a subset of the cells in the group that were programmed later than the interfered cell.

31. The apparatus according to claim 29, wherein the processor is coupled to increase the pass voltages iteratively until meeting a condition indicating that the BPD distortion is canceled.

32. The apparatus according to claim 31, wherein the processor is coupled to store the pass voltages for which the condition was met, and to apply the stored pass voltages when performing a subsequent read operation on the group of cells.

33. The apparatus according to claim 29, wherein the processor is coupled to copy the data stored in the group to another group of the memory cells after reading the second storage value from the interfered cell using the increased pass voltages.

34. The apparatus according to claim 29, wherein the processor is coupled to read the second storage value from the interfered cell multiple times while applying respective different values of the pass voltages to the gates of the other cells in the group, and to select one of the read second storage values having a lowest level of the BPD distortion.

35. The apparatus according to claim 21, wherein the cells in the group are connected in series to one another, wherein the processor is coupled to read the second storage value from the interfered cell by applying a read voltage to a gate of the interfered cell, applying pass voltages to respective gates of the other cells in the group and measuring a current flowing through the cells responsively to the applied read voltage and pass voltages, and to cancel the BPD distortion by reducing at least one of the pass voltages while not violating a predefined performance criterion, and reading the second storage value from the interfered cell using the reduced pass voltages.

36. The apparatus according to claim 21, wherein the processor is coupled to process the read second storage values so as to identify one or more over-programmed cells among the memory cells in the memory, to store information regarding the identified over-programmed cells, and to process the stored information regarding the over-programmed cells with regard to the read second storage values so as to cancel the BPD distortion.

37. The apparatus according to claim 36, wherein the processor is coupled to estimate the BPD distortion based on the stored information and to subtract the estimated BPD distortion from the second storage value read from the interfered cell.

38. The apparatus according to claim 36, wherein the processor is coupled to encode the data with an Error Correction Code (ECC), to calculate metrics for decoding the ECC based on the stored information, and to decode the ECC responsively to the metrics.

39. The apparatus according to claim 21, wherein the processor is coupled to measure shifts in one or more of the second storage values read from a subset of the cells in the group, which occurred after the cells were programmed, and to estimate the BPD distortion responsively to the measured shifts.

40. The apparatus according to claim 21, wherein the processor is coupled to encode the data with an Error Correction Code (ECC), to compute metrics for decoding the ECC based on the detected BPD distortion, and to decode the ECC responsively to the metrics so as to reconstruct the data.

41. A data storage apparatus, comprising:

a memory, which comprises multiple analog memory cells; and

a processor, which is coupled to store data in the memory by writing first storage values to the cells so as to cause the cells to hold respective electrical charge levels, to read, after storing the data, second storage values from at least some of the cells, including at least one interfered cell that belongs to a group of cells, to detect and cancel a Back Pattern Dependency (BPD) distortion caused by the electrical charge levels of one or more interfering cells in the group to at least one of the second storage values read from the at least one interfered cell, and to process the second storage values, including the at least one of the second storage values in which the BPD distortion was canceled, so as to reconstruct the data.