MEMORY SYSTEM AND METHOD OF CONTROLLING THE SAME

• US 20080219078A1
• Filed: 02/27/2008
• Published: 09/11/2008
• Est. Priority Date: 02/28/2007
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kamiyama, Yohei
• Granted Patent: US 7,596,048 B2
• Time in Patent Office: Days
• US Class Current: 365/226
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence

Abstract

One aspect in accordance with the present invention provides a memory system receiving a power supply from a host device. The memory system includes a non-volatile semiconductor memory and a controller for controlling writing and reading data to and from the semiconductor memory. The controller operates in such a manner that an amount of each of n currents is deducted from an amount of a current supplied from the power supply, the n currents having n values that gradually increase from the first to n-th.

Claims

1. A memory system receiving a power supply from a host device comprising:

a non-volatile semiconductor memory; and

a controller for controlling writing and reading data to and from the semiconductor memory, in response to a request from the host device,

wherein the controller operates in such a manner that an amount of each of n currents is deducted from an amount of a current supplied from the power supply, the n currents having n values that gradually increase from the first to n-th (n is a natural number equal to or larger than

     2);

when an amount of each of the n currents is deducted from an amount of a current supplied from the power supply in order from the first to n-th values, the controller determines whether or not the corresponding voltage of the power supply falls below a preset detection voltage; and

after detecting that a current having the p-th (p is a natural number between 2 and n, inclusive) one of the n values makes the corresponding voltage of the power supply to fall below the detection voltage, the controller operates so that the memory system consumes a current having a value smaller than the p-th one of the n values.

2. The memory system according to claim 1, wherein the n values are generated by creating states where the memory system consumes currents each corresponding to an operation thereof.

3. The memory system according to claim 1, further comprising a current consumption circuit,

wherein the n values are set in advance, and are generated by the current consumption circuit.

4. The memory system according to claim 1, further comprising a determination circuit for determining whether or not a voltage of the power supply falls below a semi-detection voltage higher than the detection voltage,

wherein the controller has a function to measure a slope of a change in the voltage of the power supply, while an amount of one of the currents having the n values is deducted from an amount of a current supplied from the power supply, by using both a difference between the detection voltage and the semi-detection voltage, and a time length between a point where the voltage of the power supply falls below the semi-detection voltage and a point where it falls below the detection voltage.

5. The memory system according to claim 1, wherein after detecting that a current having the p-th one of the n values makes the corresponding voltage of the power supply to fall below the detection voltage, the controller issue a reset signal to the host device.

6. The memory system according to claim 1, wherein the memory system operates so as to consume a current having a value equal to or smaller than the (p−

1)-th value is achieved by selecting what combination of processes to perform in parallel and by changing an operating frequency of the controller, the processes to be combined including;

wiring data in the semiconductor memory, reading data from the semiconductor memory, erasing data from the semiconductor memory, and the controller'"'"'s preparing an instruction of writing data to the semiconductor memory.

7. The memory system according to claim 1, wherein the memory system operates so as to consume a current having a value equal to or smaller than the (p−

1)-th value is achieved by single writing processing while operating the controller at the lowest frequency.

8. The memory system according to claim 7, wherein the memory system operates so as to consume a current having a value equal to the p-th value is achieved by either or both of simultaneous reading/writing processing and operating the controller at a frequency higher than the lowest system frequency.

9. The memory system according to claim 8, wherein the memory system operates so as to consume a current having a value equal to the (p+1)-th value is achieved by either or both of simultaneous writing processing and operating the controller at a frequency higher than the system frequency in the operating state where the memory system operates so as to consume a current having a value equal to the p-th value.

10. A memory system receiving a power supply from a host device comprising:

a non-volatile semiconductor memory; and

a controller for controlling writing and reading data to and from the semiconductor memory, in response to a request from the host device,

wherein the controller operates in such a manner that an amount of each of n currents is deducted from an amount of a current supplied from the power supply, the n currents having n values gradually increasing from the first to n-th (n is a natural number equal to or larger than

     2);

when an amount of each of the n currents is deducted from an amount of a current supplied from the power supply in order from the first to n-th values, the controller determines whether or not the corresponding voltage of the power supply falls below a preset detection voltage; and

after detecting that a current having the p-th (p is a natural number between 2 and n, inclusive) one of the n values makes the corresponding voltage of the power supply to fall below the detection voltage, the controller operates so that the memory system consumes a current having a value obtained by multiplying a value smaller than the p-th one of the n values by a common value larger than 1.

11. The memory system according to claim 10, wherein the n values are generated by creating states where the memory system consumes currents each corresponding to an operation thereof.

12. The memory system according to claim 10, further comprising a current consumption circuit,

wherein the n values are set in advance, and are generated by the current consumption circuit.

13. The memory system according to claim 10, wherein after detecting that a current having the p-th one of the n values makes the corresponding voltage of the power supply to fall below the detection voltage, the controller issue a reset signal to the host device.

14. The memory system according to claim 10, wherein the memory system operates so as to consume a current having a value equal to or smaller than the (p−

1)-th value is achieved by selecting what combination of processes to perform in parallel and by changing an operating frequency of the controller, the processes to be combined including;

wiring data in the semiconductor memory, reading data from the semiconductor memory, erasing data from the semiconductor memory, and the controller'"'"'s preparing an instruction of writing data to the semiconductor memory.

15. A method of controlling a memory system, the memory system including a non-volatile semiconductor memory and a controller for controlling writing and reading data to and from the semiconductor memory, in response to request from the host device, comprising:

deducting an amount of each of n currents from an amount of a current supplied from the power supply, the n currents having n values that gradually increase from the first to n-th (n is a natural number equal to or larger than

     2);

determining whether or not the corresponding voltage of the power supply falls below a preset detection voltage when an amount of each of the n currents is deducted from an amount of a current supplied from the power supply in order from the first to n-th values; and

operating so that the memory system consumes a current having a value smaller than the p-th one of the n values after detecting that a current having the p-th (p is a natural number between 2 and n, inclusive) one of the n values makes the corresponding voltage of the power supply to fall below the detection voltage.

16. The method according to claim 15, further comprising:

generating the n values by creating states where the memory system consumes currents each corresponding to an operation thereof.

17. The method according to claim 15, wherein the n values are set in advance.

18. The method according to claim 15, further comprising:

determining whether or not a voltage of the power supply falls below a semi-detection voltage higher than the detection voltage, and

measuring a slope of a change in the voltage of the power supply, while an amount of one of the currents having the n values is deducted from an amount of a current supplied from the power supply, by using both a difference between the detection voltage and the semi-detection voltage, and a time length between a point where the voltage of the power supply falls below the semi-detection voltage and a point where it falls below the detection voltage.

19. The method according to claim 15, further comprising:

issuing a reset signal to the host device after detecting that a current having the p-th one of the n values makes the corresponding voltage of the power supply to fall below the detection voltage.

20. The method according to claim 15, further comprising:

selecting what combination of processes to perform in parallel and changing an operating frequency of the controller so as to consume a current having a value equal to or smaller than the (p−

1)-th value,

wherein the processes to be combined including;

wiring data in the semiconductor memory, reading data from the semiconductor memory, erasing data from the semiconductor memory, and the controller'"'"'s preparing an instruction of writing data to the semiconductor memory.